Remove DCM wrappers from EDK designs

Hi,

I'm working on a partial reconfiguration design and need to validate an assumption.

This question isn't directly releated to partial reconfigration, so don't let that scare you away.

I have a MicroBlaze created in EDK 8.2 that I must be integrate into a top level design created in ISE 8.2. I'm using the Virtex II-Pro.

The methodology is to take the system.vhd generated by EDK during netlist generation and add these component declarations and instantiations to the top level design. In a partial reconfiguration design clock primitive must be in the top level design. However, the system.vhd file uses wrappers for DCMs. Here's my question...am I removing the DCM wrapper correctly?

I remove the wrapper component declarations by commenting them out (I only show one here):

-- component dcm_0_wrapper is

-- port (

-- RST : in std_logic;

-- CLKIN : in std_logic;

-- CLKFB : in std_logic;

-- PSEN : in std_logic;

-- PSINCDEC : in std_logic;

-- PSCLK : in std_logic;

-- DSSEN : in std_logic;

-- CLK0 : out std_logic;

-- CLK90 : out std_logic;

-- CLK180 : out std_logic;

-- CLK270 : out std_logic;

-- CLKDV : out std_logic;

-- CLK2X : out std_logic;

-- CLK2X180 : out std_logic;

-- CLKFX : out std_logic;

-- CLKFX180 : out std_logic;

-- STATUS : out std_logic_vector(7 downto 0);

-- LOCKED : out std_logic;

-- PSDONE : out std_logic

-- );

-- end component;

-- attribute box_type of dcm_0_wrapper: component is "black_box";

-- Then I change the dcm instantiations only change the component name from "dcm_0_wrapper" and "dcm_1_wrapper" to dcm. dcm_0 : dcm -- changed from dcm_0_wrapper port map ( RST => net_gnd0, CLKIN => dcm_clk_s, CLKFB => sys_clk_s(0), PSEN => net_gnd0, PSINCDEC => net_gnd0, PSCLK => net_gnd0, DSSEN => net_gnd0, CLK0 => sys_clk_s(0), CLK90 => clk_90_s(0), CLK180 => open, CLK270 => open, CLKDV => open, CLK2X => open, CLK2X180 => open, CLKFX => open, CLKFX180 => open, STATUS => open, LOCKED => dcm_0_lock, PSDONE => open ); dcm_1 : dcm -- changed from dcm_1_wrapper port map ( RST => dcm_0_lock, CLKIN => ddr_feedback_s, CLKFB => dcm_1_FB, PSEN => net_gnd0, PSINCDEC => net_gnd0, PSCLK => net_gnd0, DSSEN => net_gnd0, CLK0 => dcm_1_FB, CLK90 => ddr_clk_90_s(0), CLK180 => open, CLK270 => open, CLKDV => open, CLK2X => open, CLK2X180 => open, CLKFX => open, CLKFX180 => open, STATUS => open, LOCKED => open, PSDONE => open ); Do anyone know if this dcm will behave the same way as it would have using the wrapper for the Virtex II Pro? I have memory problems that I can't track down so I'm trying to make sure this changes doesn't effect how the memory and microprocessor are clocked. Thanks, David