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Registers replication on Xilinx IOBs

Dear all, when synthesizing my design with XST, i get some messages like this one; "Flip-flop ... has been replicated 1 time(s) to handle iob=true attribute". The replicated flip-flops have their output shared between internal logic and IO pins. I understand that this replication could improve IO performances and that is the reason for adding such flip-flops on IOB. Am I right ?

Moreover, both XST and Precision RTL show the same behavior in synthesis (under the default synthesis settings), so it seems this replication is strongly recommended. Can someone clarify this point ?

Thanks in advance,

Giuseppe

Reply to
giachella.g
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In this case, the replication of the flip-flop is architecturally required in order to satisfy the iob=true attribute.

The Q output of the output flip-flops in the IOBs connect ONLY to the output driver for the pin. There is NO other route available to this signal - it MUST go off chip. Since your HDL specifies connectivity both to the output pin as well as to internal logic, the synthesis tools must replicate them.

Since the Q output of the IOB flip flop cannot connect to internal logic, and you have specified that the flip-flop driving the output pin must be in the IOB, the tools have to create two flip flops; one internally in the "core" of the FPGA (in a slice), so that the Q output of this flip flop can drive the internal connections you have asked for, and a second one in the IOB to drive the output pin.

Avrum

Reply to
Avrum

If you place all flip-flops on a bus in the IOBs, then the only timing stuff you have to worry about is the clock to out parameter (with maybe a bit of clock skew, package skew - small effects). If you don't put them in the IOBs then they are somewhere in the fabric - with potentially widely varying times to get from the flip-flop to your output. Secondly, if they are in the general fabric and they are not locked down, then their position may vary across synthesis/p&r runs, generating inconsistant results.

Jeremy

Reply to
Jeremy Stringer

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Howdy Avrum,

Actually there is a route available - how else would bi-directional I/O's work? It's true that the tools typically don't do this (probably for signal integrity and prop delay time reasons), but it can be done.

Have fun,

Marc

Reply to
Marc Randolph

It doesn't do it because the signal would take longer to travel tha path than if it's replicated, but also for more obvious reasons, an I exaplin..

The signal at output of IOB register is not garanteed to be the signa

that would get to the input, after it passed via the IO pad net. There's a lot of external interference that can occur, such as noise .. Another example is if the output is sink-only (open-drai output). The IOB register may output a 1, while the IO pin is drive a zero (by an external driver sharing the same trace). This can eve also occur with push-pull output, if there's (for some reason contention on the IO pin

So, for those reasons, if a register need feedback to the FPGA fabric

but also require low output skew, then register replication is th only solution. To avoid warning, you could replicate the register i your source code, but this could make the code more obscure. Yo could always put a comment that specify that this extra register i for FPGA IOB register, the other for feedback

Reply to
Big Boy

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