Hi,
I've been using X FPGA for years and I often use the following VHDL initial value assignment, especially for finite state machines, counters, etc :
signal sCounter : std_logic_vector(7 downto 0) := x"1B";
Using "FPGA Editor", I'm able to validate that the synthesis tool has correctly interpreted the initial value by checking individual slice FF (INIT0, INIT1).
Now, my problem. Not having much experience with A Stratix II FPGA, I'm a little confused about how the synthesis and fitter tools use the initial value assignment. Quartus has a synthesis option of "Power-up Don't Care" that can be turned off. Does that means that FF must be initialized using the Assignment Editor using "Power-Up Level" attribute? RTFM didn't help (Quartus II 6.1 Handbook, Stratix II Device Handbook). Also, I tried to check the result with "Chip Editor" but the FF power-up values are not indicated (or I simply don't know how to show them) so I can't validate power-up conditions. For the moment, I don't have access to the hardware (else I would have already made a simple test to check that issue).
Anyone has a hint about how Quartus Synthesis handle initial values assignments?
Thanks!