Regional Clock Network and Large Designs

Hello,

I'm getting usual results from my BUFR network in Timing Analyzer:

-------------------------------------------------------------------------------- Hold Violations: TS_adc1_dclk_p = PERIOD TIMEGRP "TG_adc1_dclk_p" 4 ns HIGH 50%;

-------------------------------------------------------------------------------- Hold Violation: -0.974ns (requirement - (clock path skew + uncertainty - data path)) Source: adc1_reg_inst/nshifts_gen[1].dff_ins/d_r_7 (FF) Destination: adc1_reg_inst/nshifts_gen[2].dff_ins/d_r_7 (FF) Requirement: 0.000ns Data Path Delay: 1.275ns (Levels of Logic = 0) Positive Clock Path Skew: 2.249ns Source Clock: adc1_dclk rising at 0.000ns Destination Clock: adc1_dclk rising at 4.000ns Clock Uncertainty: 0.000ns Timing Improvement Wizard Data Path: adc1_reg_inst/nshifts_gen[1].dff_ins/d_r_7 to adc1_reg_inst/nshifts_gen[2].dff_ins/d_r_7 Delay type Delay(ns) Logical Resource(s) ---------------------------- ------------------- Tcko 0.268 adc1_reg_inst/nshifts_gen[1].dff_ins/ d_r_7 net (fanout=1) 1.065 adc1_reg_inst/d_array Tckdi (-Th) 0.058 adc1_reg_inst/nshifts_gen[2].dff_ins/ d_r_7 ---------------------------- --------------------------- Total 1.275ns (0.210ns logic, 1.065ns route) (16.5% logic, 83.5% route)

2.25 ns positive clock path skew? Omg!? So, then I looked at the partially PAR'ed output on this SX55 FPGA. Turns out the stupid tools are expanding the BUFR network across multiple BUFR regions, including horizontally (x direction). I have an 8k FIFO (necessary) to transition from this BUFR clock to a slower BUFG clock. Looks like the tools are placing the FIFO on the left side of the FPGA and the top- right BUFR is using non BUFR resources (I assume) to route the clock across.

Is this what's causing my enormous clock path skew? I will try to apply some area_group slice/bram constraints to my FIFOs, but I find this to be an extreme pain in the butt... I'm using a COTS board, which is configured with 4 ADC data channels and 4 ADC clocks. The ADC data is about 180 degrees out of phase w/ the clock (fine). Is there a way to constrain nets/instances/etc. to a regional clock region? That'd be really sweet...

Is there a better way to transition from the regional clock to a global clock other than using a FIFO? This is giving me a headache b/c my design takes forever to PAR and I can't meet timing :(

Thanks,

-B