i have done the post place and route timing simulation for my design. i am getting the following warnings . there is a setup time voilation but can any one explain what this statment means
Time: 4785 ps Iteration: 2 Instance: /sts3c_top_tb/dut/ deframer_inst_fifo_inst_bu236 # ** Warning: /X_SFF SETUP High VIOLATION ON SRST WITH RESPECT TO CLK; # Expected := 0.748 ns; Observed := 0.653 ns; At : 4.785 ns
is that my data is arriving early than the expected ... can any one explain me what that warnings means and how can i make sure in my design to avoide this kind of warning .. that does this kind of warning do matter when i am loading my design into silicon. as my design is not working on the actual silicon.
Hi, SRST signal changes its value to close in time to the active edge of clock CLK. It should be changed at least 0.748 ns before the active edge. But the change appears
0.653 ns before the active edge. The violation is detected at 4.785 ns simulation time (It is probably beginning of the simulation).
You are probably applying reset in the testbench at the same time when an active clock edge appears. The reset should be applied some time after an active clock edge. This is the most frequent reason of that. There are also many other possible reasons: - you are clocking the design with too high frequency. - the clock is significantly delayed in you design (big clock skew) - the reset signal is crossing different clock domains..etc.
i am usign clokc of 155Mhz(6.43 ns) and in my testbench i am doing reset after 100 ns (intially it is '0' then it is '1' after 100 ns delay) is this the reason for my warnings. but this is in testbench and actual design should not be get effected by this right and it may not effect in the actual silicon....
All constraints were met. INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 6 mins 16 secs Total CPU time to PAR completion: 2 mins 44 secs
Peak Memory Usage: 322 MB
Placement: Completed - No errors found. Routing: Completed - No errors found. Timing: Completed - No errors found. this what the timing report after place and route.......
Hi, as I mentioned there are many of possible reasons.
Regarding the timing violation. You can check inputs of the /sts3c_top_tb/dut/deframer_inst_fifo_inst_bu236 flip-flop and track the change to find its source. However, such violation at the beginning of the reset may not be relevant.
I am guessing but if your design incorporates LVDS transmission module working on both clock edges (DDR) quality of the clock is essential, for instance jitter, duty cycle, phase shift (comparing to clock phase in external receivers and transmitters) etc. Such things are not modeled very well in simulation and you may be surprised why it is working in simulation but not in the real silicon.
This is all what I can guess without knowing your design.
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