regarding the clock issues in the fpga...

hi all,

i have got one problem:

i have designed sonet sts-3c framer/deframer where it works at 155mhz freq which i am getting it form the optics card whrere CDR(clock data recovery circuit outside the board). form that circuit i am getting the differential data and differetial clock as inputs and i am processing for output (differential data). which iam sending it to optics card which will convert the electrical diff data into optical signal and it is recongniged in the OmniBer (performace analyzer). my problem is as i am getting the data and the clock i have a problem in detecting the output on OMNIBER but my logic looks quiet ok.

i am using virtex - 2pro fpga which can support 155mhz clock.......

i have done small experiment by looping it back the data ... with out processign ... just what ever the optics card send the data (diff data input) i am looping inside the fpga and sending it back ... that time it detecting in omniber . but same exp if i am doing with respect to clock i am unble to detect the framer in the omniber.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

-- synthesis translate_off library unisim; use UNISIM.Vcomponents.ALL; -- synthesis translate_on

entity loopback is port ( rxdata_in_p : in std_logic; rxdata_in_n : in std_logic; txdata_out_p : out std_logic; txdata_out_n : out std_logic ); end loopback;

architecture rtl of loopback is

signal txdata : std_logic; signal txdata_out : std_logic; signal rxdata_in : std_logic;

--

****************************************************************-- -- ***************************IBUFDS******************************* -- -- ****************************************************************-- component IBUFDS port (O : out STD_ULOGIC; I : in STD_ULOGIC; IB : in STD_ULOGIC); end component;

--

****************************************************************-- -- ***************************OBUFDS******************************* -- -- ****************************************************************-- component OBUFDS port ( O : out STD_ULOGIC; OB : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Black box declaration -- attribute syn_black_box : boolean; attribute syn_black_box of OBUFDS: component is true;

begin

--IBUFGDS_INSTANCE_NAME : IBUFGDS --port map (O => clk155p52, -- I => clk155p52_p, -- IB => clk155p52_n);

IBUFDS_INSTANCE_NAME : IBUFDS port map (O => rxdata_in, I => rxdata_in_p, IB => rxdata_in_n );

txdata_out txdata_out_p, OB => txdata_out_n, I => txdata_out );

end rtl;

just what ever i am getting the diff data as input i am giving to output that all to ensure that the fpga path is fine.if the same thing i am doing wrt to the clock diff i am not able to detect the data send in the omniber .

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

-- synthesis translate_off library unisim; use UNISIM.Vcomponents.ALL; -- synthesis translate_on

entity loopback is port ( porstn : in std_logic; --clk155p52 : in std_logic; clk155p52_p : in std_logic; clk155p52_n : in std_logic; rxdata_in_p : in std_logic; rxdata_in_n : in std_logic; txdata_out_p : out std_logic; txdata_out_n : out std_logic ); end loopback;

architecture rtl of loopback is

signal txdata_out : std_logic; signal clk155p52 : std_logic; signal rxdata_in : std_logic;

--

******************************************************************-- -- ****************************IBUFGDS********************************-- component IBUFGDS port (O : out STD_ULOGIC; I : in STD_ULOGIC; IB : in STD_ULOGIC); end component;

--

****************************************************************-- -- ***************************IBUFDS******************************* -- -- ****************************************************************-- component IBUFDS port (O : out STD_ULOGIC; I : in STD_ULOGIC; IB : in STD_ULOGIC); end component;

--

****************************************************************-- -- ***************************OBUFDS******************************* -- -- ****************************************************************-- component OBUFDS port ( O : out STD_ULOGIC; OB : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Black box declaration -- attribute syn_black_box : boolean; attribute syn_black_box of OBUFDS: component is true;

--component sts3c_test --port( -- clk155p52 : in std_logic; -- porstn : in std_logic; -- dataout : out std_logic -- ); -- end component;

begin

IBUFGDS_INSTANCE_NAME : IBUFGDS port map (O => clk155p52, I => clk155p52_p, IB => clk155p52_n);

IBUFDS_INSTANCE_NAME : IBUFDS port map (O => rxdata_in, I => rxdata_in_p, IB => rxdata_in_n );

--sts3c_inst: sts3c_test --port map ( -- clk155p52 => clk155p52, -- porstn => porstn, -- dataout => rxdata_in -- );

process(porstn,clk155p52) begin if(porstn ='0') then txdata_out

Reply to
ekavirsrikanth
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FPGAs are not precision analog components. The jitter produced by an FPGA will be large compared to SONET jitter specifications. If your "omniber" is not tolerant to this excessive jitter, your results may not be what you want.

Please clarify: if pass the data from the omniber to the FPGA and back to the omniber, are your results fine? That wasn't clear.

Is your problem that the loopback data *is* fine but your own frame logic is not?

Do you know what portion of the frame and payload is scrambled and what is not?

Reply to
John_H

hi john thank you for u r valuble reply...

intially what i am trying is i just wnated to detect the framing bytes .. in the omniber... rest of the things i will take care once the logic doesnot show any pattern loss in the omniber.

i am taking the sonet frames form the omniber and at this point of time i am not descrambling (in deframer) or scrambling (in framer).just taking what ever omniber is sending then detecting the framer bytes(a1 and a2 bytes) and then allowing the rest of the payload and other overhead. on detecting the framing bytes i am sending rest of data through fifo and then passign the data to the framer part. in the framer side just inserting the a1 and a2 bytes and other overhead bytes and just allowing the payload that i got form deframer. then sending it to optics card to omniber.

now my loopback (which i have done for just checking if data is processign wrt the clock) is working the second code which i have posted before but my sts3c deframer/framer logic is not working as i am usign the clock (derived form the optics card) somany places in the design is that creating any problem any clock related issues are there......

regards srik

Reply to
ekavirsrikanth

If loopback works but your framer/deframer does not and the clock is the same in both cases, you have a logic problem that the omniber doesn't like.

If your loopback works without reclocking the data but the loopback doesn't work if you do reclock the data, you have a clock problem.

Isolation of the problem is key to debugging.

I'm concerned that your payload and the rest of the frame may be descrambled/scrambled incorrectly in the setup where the omniber has trouble detecting valid frames. It's quite possible the omniber uses more than just the a1/a2 framing words at the correct repetition location to declare a valid frame. It's that extra information that it can't correctly decode.

At least that's what I feel might be going on here.

Reply to
John_H

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