Hi experts, Hi all i need a help,I am using the spartan
FPGA.I am using the DCM to scale the input clock frequency
to 72Mhz.This clock signal is feed to the sram in the
board,which is also the system c*ck.When i analyse the timing report the clock to pad
delay for the port sram_clk[clk output from DCM to SRAM]
is not mentioned in the report. Could any one help me in finding the clock to pad delay in the timing report.