Recursive component instantiation

Does synplify support recursive component instantiation, i.e. a component which instantiate its own entity within its architecture...

Reply to
Patrik Eriksson
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Yes, and it has since at least 4.2, although there have been occasionally some hiccups with some versions. If you run into a problem,however, don't expect to get much help from their tech support regarding recursion. I never was able to get their hotline engineer to understand why I wanted to recurse and not just construct with direct instantiation.

Reply to
Ray Andraka

I don't wish to hijack your thread, but what would you use recursive component instantiation for? are you instantiating within an instantiation?

Cheers

david

Reply to
googlinggoogler

Given that synplify (and any other synthesis tool that supports recursion) requires the recursion to be staticly bound, there is always a way to describe a recursive solution with loops. Often the recursive form is easier to understand.

They have to be staticly bound so that synthesis can unroll the recursion to a determinately finite end.

Recursion can be done with instantiating using if-generate statements that conditionally instantiate themself, which by definition are staticly bound.

Recursion can also be done with function or procedure calls that conditionally call themself.

Andy

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Reply to
Andy

Sometimes a parameterized component is easiest to generate with recursion. For example an adder tree can be generated by recursively calling a component that adds two vectors.

Reply to
Ray Andraka

Thank you all for the answers.

The example with a parameterized component is exactly what I have designed. I have a generic component that implement the looping algorithm used to calculate the configuration bits for a Benés network with a generic number of ports. The lowest level is for a 4-port Benés network. For each hierarchal level the number of ports are doubled. I have simulated my code in modelsim and it have the correct behavior but in synthesis I get a width mismatch for one of the output ports. Unfortunately no figures of the different widths are printed by synplify so I can't know at which level the error occurs. But from your answers I now know that synplify should fix this. Maybe it could be a problem with how generics are handled (global or local?)

Thanks again!

Cheers Patrik

Reply to
Patrik Eriksson

I also like recursion in HW design, and used exactly the population count with a long vector as an educational example.

However I think that even in that case it is better to use flat instantiation and recursive functions to calculate the parameters (adder sizes), indexes for the connections of the ports and so on.

In many tools recursive instantiation has the consequence of very long unreadable signal and component names in the netlist. This makes pattern matching etc. in floorplanning, timing analysis etc. harder. By using recursive functions and flat instantiation one gets both, clarity and easy handling. In both cases it would be nice to have a standardized way to control the naming of instantiated primitives (such as adders or registers).

Andreas

Reply to
acd

Thank you all for the answers.

The example with a parameterized component is exactly what I have designed. I have a generic component that implement the looping algorithm used to calculate the configuration bits for a Benés network with a generic number of ports. The lowest level is for a 4-port Benés network. For each hierarchal level the number of ports are doubled. I have simulated my code in modelsim and it have the correct behavior but in synthesis I get a width mismatch for one of the output ports. Unfortunately no figures of the different widths are printed by synplify so I can't know at which level the error occurs. But from your answers I now know that synplify should fix this. Maybe it could be a problem with how generics are handled (global or local?)

Thanks again!

Cheers Patrik

Reply to
Patrik Eriksson

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