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$recovery

Hi, I am doing FPGA design with xilinx spartan 3e. When I finished P&R, I checked the timing report. Everything is ok, and there is no timing violations. But when I run post simulation, the modelsim reports some timing errors for some registers with $recovery(...). I checked the time when these errors occur. They happened to be the time when reset is de-assertion. I tried to change reset period, but this time other register report $recovery/$setup/$hold errors. It is very strange because I have passed P&R, there is no timing violations, why does these errors orrur? Can anybody help me? thanks very much.

Reply to
skyworld
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normally you wont have specified any time constraints on the reset signal... I aam assuming you have a global asynchronous reset.

To correctly manage the reset you should try to synchronise it to the internal clock using a couple of flip-flops. This way it ensures a synchronous release of the reset that can be treated and analysed in the same way as any other. I think you may still get the warnings for violations of the first asynchronous input.

Anyways, the idea of synchronous vs asynchronous reset is a long discussion =)

Ben

Reply to
Benjamin Todd

So do you mean that I can ignore these warnings?

.=2E.

on

Reply to
skyworld

i'd say Yes...But make sure it's only teh asynchronous reset thats causing these problems, nothing else. And even then I recommend you have a look around for debates over synch vs asynch reset... it's one of these issues that is unpredictable, and can make your circuits really misbehave... Ben

Reply to
Benjamin Todd

=C2=B7=C3=96, "Benjamin Todd"

Thanks for your help.

Reply to
skyworld

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