We are trying to implement a toplevel module which has an IN and an OUT port which are records. The synthesis works fine but we have the problem that synplify converts these record ports in a big port like "i_inputs[80:0]" instead of single ports like i_inputs.in0, i_inputs_flag, i_inputs.enable ...
This way its impossible later to assign the pins of the FPGA in Designer to the correct port. Is there anyway or work around to solve this problem or to change this behaviour?
Can the pins be assigned before synthesis? in the sdc file? And if it is possible which format do I use for the records?
Thanks and congratulations for the forum, always source of solutions!
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