Reconfiguring at runtime internally?

Hi, Is it possible to reconfigure an FPGA from 'within' the FPGA at runtime, without any need for an external system to do this? I would like to make a design that can create/remove 'components' at runtime.

Do all/any of the mainstream chips support this (Xilinx, Altera)?

Does anyone have any experience of doing this? What is the performance like? What impact does it have on the overall system? I was thinking that a core would remain constant, and pre-defined areas would be dynamically changed as required.

Also, is there any available software that will support/simulate this functionality? Preferably something that I could afford (personal hobby project) would be good!

I'm sorry if this is a bit of a newbie question. I have had a good dig around for answers, but not found anything other than hints that this can be done. Maybe. I'm looking at doing some GP work with FPGA's, as I only discovered they even existed a few days ago, and they seem suited to GP work.

Any help would be appreciated. Thanks in advance,

- Jelly.

"Beware of the Leopard!"

Reply to
Jelly
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Look at the LATTICE range of XPGA products.

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Reply to
Matt North

Virtex II and Virtex II Pro allow internal reconfiguration through the ICAP module, the application note XAPP662 as an example that shows how this could be done

Reply to
Miguel Silva

Yes, this is definitely possible using a variety of Xilinx FPGAs. Xilinx uses the term partial reconfiguration for what you're asking for, I think. Please visit the following FAQ as it probably answers most of your questions.

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--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

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--------------------------------- Spartan-3: Make it Your ASIC

Reply to
Steven K. Knapp

be

I remember a discussion on this newsgroup a while back touching ICAP and its performance. I believe it was triggered by the fact that ICAP would not be in the Spartan3 chips. You might want to check the archives...

--
Pierre-Olivier

-- to email me directly, remove all _N0SP4M_ from my address --
Reply to
PO Laprise

Just a clarification -- the Internal Configuration Access Port (ICAP) is available on some Xilinx FPGAs to aid reconfiguration from within the device. However, devices without ICAP can still be partially reconfigured from internal logic.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

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--------------------------------- Spartan-3: Make it Your ASIC

ICAP

could be

Reply to
Steven K. Knapp

Did you mean to write "from external logic"?

There's also another way it could be done, for non-ICAP devices. Basically just feed some user IO back into the external SelectMAP pins, and create bitstreams with the -g Persist:yes option to keep the selectMAP interface alive after configuration.

Your self-reconfig core then drives those user pins (and thus the selectMAP interface) as required.

This costs a few pins and requires planning at the board design stage, but if you need self-reconfig that badly in a non-ICAP device, then it seems a feasible approach. Have I missed anything?

Regards,

John

Reply to
John Williams

I believe the maximum speed of the external SelectMAP interface is also greater than that of the internal ICAP, for some reason, allowing for faster reconfiguration by looping off-chip than by staying on-chip... (working from memory, take it for what it's worth)

--
Pierre-Olivier

-- to email me directly, remove all _N0SP4M_ from my address --
Reply to
PO Laprise

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