Hello,
I have a question about the modular design flow for partial reconfiguration.
I created a small pr demo using xilinx modular design flow for a virtex2pro fpga.
It consists of 2 static parts with 1 reconfigurable area between. The logic functions of the modules are kept simple stupid. ;-)
Intermodule communication happens over a bus macro.
All i/o-pads (including the external clock) are located inside the area of the static module on the right side.
The one and only clock signal is shared by the reconfigurable module in the middle and the right static module.
Following XAPP290 and all pursuing papers I've read, clock signals aren't routed explicitly over bus macros. Thus they are distributed over the global clocking network resources, right?
But while active module phase, I encountered the suspicious warning, that PAR has noticed one unrouted signal. Taking a look at the partial netlist inside the FPGA_EDITOR - e.g. the one for the reconfigurable module in the middle - this could be verified. The clock signal was an unrouted net.
Is this normal or what am I doing wrong? Shouldn't the clock signal for the reconfigurable module be routed inside its area to an global clock resource connection?
I can't imagine, that the obtained partial bitstream from the netlist of the reconfigurable module is going to configure correctly, when the clock signal isn't somehow routed.
Could this problem be caused by missing LOC-constraints for the IBUFG and BUFG in the constraint file? Is this necessary at all. Should all I/O-BUFs be LOC-constrainted for partial reconfiguration based on modular design flow?
Any suggestions, experiences or in-depth explanations are appreciated. *thx*