Recommendation for creating a DDR Sdram core for custom board and integrate in XPS

If I understand your question correctly, take a look at the reference design at the link below. It shows how to close the feedback loop internally. I guess, depending on the hardware, you might need to introduce some delay in this path...

XMD has nothing to do with the core. What exactly are you going to implement? Integrating a peripheral into XPS isn't that difficult. Copy the PLB_DDR core from the %Xilinx_EDK\hw\XilinxProcessorIPLib\pcores\ directory into your projects pcores directory and edit the source files however you want. Restart XPS or rescan project repositories, XPS will pick up the local version of the core instead of the one in the EDK tree.

/Mikhail

Thanks for your reply.

Respect to the project you send me, I cannot see the vhdl code related to the ddr control. Where do I look for?.

Once again I am very grateful for your help

Regards

When you design with EDK you don't normally need to go down to VHDL or Verilog code unless you are designing your own cores. In the case of the design I mentioned, all of the cores are from the Xilinx EDK library (the PLB_DDR core is for sure from the EDK library), so there isn't really any need to look for the code. To see how the cores are connected take a look at the system.mhs file.

/Mikhail

What about the phase difference?. I suppose that there is a little skew resolve by the feedback, but it seems that internal feedback clock is the same of the proccesor?.

Regards again

Exactly, the purpose of the feedback must be to compensate for the skew, however it is probably small enough on this particular board that it can be ignored.

/Mikhail

I have probed this method on a Spartan 3E starter kit ( another board used for testing) and works fine. At the moment the custom board doesn't work, but it is possible that exists this few skew. Is it a method to apply a phase to a plb_ddr core?

Pablo

Would you mind to share the code you used on the spartan 3e kit ?