realize pci in fpga

hi,all. I am realize pci target core in fpga(cyclone),but there are some questions.

1,I don't know what type pin should pci_clk be,normal io or clk of fpga? 2,I series 50ohm resistors between pci connector and fpga,does this bring some problems? the goal is to make it suitable for 3.3v and 5v. thanks.
Reply to
eehinjor
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Cyclone is not compatible with PCI 5v, the voltage transients exceed 5v and will damage the device.

You will need to use IDT Quickswitch or similar device to limit the input voltage to your Cyclone in a 5v scenario.

Google for PCI and quickswitch, you should find a Xilinx app's note on the subject.

Alan

Reply to
Alan Myler

... or look a the schematics for the Altera Cyclone PCI development kits.

-hpa

Reply to
H. Peter Anvin

Finding is better than looking....

ftp://ftp.altera.com/outgoing/devkit/PCI_DK_2C35/schem_cii_pcidevbd_b.pdf

Karl.

Reply to
Karl

Thanks all.

risistors.

Can somebody help me to solve the first question?

Reply to
eehinjor

Making the clock track longer gives you better setup but reduces your hold time on data getting written to your chip.

For reads from your chip (or DMA writes), you have to make sure your clock to out timings allow for two types of extra delay. First is getting through the bus switch. Second is the extra delay because your clock is late because it is going through the bus switch on the way in.

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Reply to
Hal Murray

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