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Real-world soft-cpu performance

Hi all,

So, before I splash out on the EDK, I'd really appreciate some advice on what the real MHz limits are on the microblaze (almost certainly in a Spartan-3E). From the webpage it says it'll do 100MHz but then qualifies it as execution from BRAM only. Questions...

- Does the 100 MHz figure imply a 100 MHz bus-speed too ? I see a bunch of tutorials where the bus is only 66MHz.

- How does the system scale as you add more PLB peripherals, or OPB ones for that matter

- If I make a peripheral, do I get bus-mastering built-in (or at least supported) with the tools provided ? It would be useful for more than one peripheral to access the SDRAM controller, for example :-)

- If I can persuade myself to splash the cash on a V4FX design instead, what sort of real-world MHz am I looking at for the PPC chip ? Again, it claims 450MHz in the datasheets, but is that realistic ?

Since this is only a hobby, $500 is a large chunk of pocket-change so I'd be very grateful for answers to the above. If (as I've been told) it's typically "difficult" to get 100MHz from a microblaze (with h/w multiplier, barrel shifter, SDRAM interface, and a couple of peripherals), I may look at using the FPGA to interface with an external coldfire at 147MHz instead, and then I might not need the EDK, though unit costs of the board will be more expensive...

Thanks in advance,

Simon

Reply to
Simon Gornall
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Simon Gornall schrieb:

Hi Simon,

67(or 75) are most suitable candidates for the system and bus clocks. ML40x board reference designs from Xilinx that include a big bunch of peripherals are supposed to run at sysclock 100MHz but it may take an eternity in place and route. So 75MHz way more easy to obtain.

MicroBlaze 5 may get little fmax performance but I havent yet real comparison values.

Adding more peripherals makes it harder to meet timing, so system fmax goes lower in generic.

As of multiply access to SDRAM it may be easier to add your peripherals not to the PLB/OPB bus but to the XCL ports of the multichannel SDRAM controller. So the high speed access is streamed directly to SDRAM controller.

The claims for microblaze and ppc fmax have to be read with some precaution. In April 2006 Xilinx claimed 200MHz fmax for MicroBlaze 4 in Virtex-4. Maybe it is possible under some conditions but for me it sounds like wishfull thinking. Well I bet MB 5 in Virtex5 in "ultracontroller" like setup may run at 200MHz - this is more realistic. But some small medium MB.4 system in Virtex-4 does not reach

200MHz (at least with current XST synthesis, maybe XST will improve timing once again and get better performance). Similarly the 450MHz PPC operation defenetly means operation from onchip caches only with no bus peripherals at all. So for real applications you better calculate with 300MHz cpu clock.

But - the type of hardcore CPU in Virtex-5FX is not yet known. It is not the same core that is in v2pro-v4, so what we can expect there is to be seen.

Antti

Reply to
Antti

Hi Antti,

which speed-grades are you talking about? Slowest or fastest?

Thomas

"Antti" schrieb im Newsbeitrag news: snipped-for-privacy@i3g2000cwc.googlegroups.com...

Reply to
Thomas Entner

Thomas Entner schrieb:

Thomas,

the fmax info for each FPGA SoC system should be really checked case by case, and 75MHz is generically good choice. it may be possible to get 100Mhy timing ok in slowest speed and it maybe that frequencies below 100MHz make problems in highest speed grade.

so make the system, add the peripheral and run synthesis to see what goes.

Antti

Reply to
Antti

Quoth Antti

Thanks Antti - good to know :-)

Simon.

Reply to
google

So, this is probably a stupid question (it's probably in plain view, now that I'm bitching about their site [grin]), but do you have a pointer to the documentation about this SDRAM controller, and how you interface to it (I found XAPP912 :-) ? Or to any of the 'make-your-own-PLB/OPB-device' examples (I found XAPP264 as well, but I was figuring there may be a bit more somewhere, a spec, for example :-)

Xilinx sure make it hard to find stuff on their website... I only found the XAPPs above using google... You'd have thought there'd be something directly under

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...

Thanks in advance :-)

Reply to
Simon Gornall

Simon Gornall schrieb:

the XCL interface is only described in documentation supplied with the EDK, so do not look for any docs on Xilinx website.

I think the mch_ edk memory controllers could be used without EDK also with some little wrapper, but such a use is not encouraged

Antti

Reply to
Antti

Hmm. Perhaps I'd just better fork out for the EDK... Thanks for the info though :-)

ATB, Simon

Reply to
Simon Gornall

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