When you generate a core in ISE, the CoreGen tool creates a file with your module name and extension .veo (so if your core is called my_dds, you should have a file called my_dds.veo) In this file is an instantiation template for the CoreGen module. It may look like:
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG my_dds YourInstanceName ( .DATA(DATA), .WE(WE), .A(A), .CLK(CLK), .ACLR(ACLR), .RFD(RFD), .RDY(RDY), .SINE(SINE), .COSINE(COSINE));
// INST_TAG_END ------ End INSTANTIATION Template ---------
In Verilog you can't tell from the template which ports are ins, outs, vectors, scalar. You can find this information if you look into the generated simulation module my_dds.v
If you're using the project navigator, an easy way to see how to instantiate the module is to go to Project-->NewSource and make a new Verilog TestFixture associated with my_dds. This will generate a file with the instantiation template and registers and wires for the modules inputs and outputs. It may look like:
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