I'm trying to use some real constants in synthesis. I expect them to be truncated to binary values, but it appears XST doesn't like them and it also doesn't like the $realtobits() system function in verilog.
Here is a short example of what I'm trying to do:
`define CLKSPD 50 //MHz `define WTIME 43.03*`CLKSPD //Wait Time is 43.03us (approximately)
module wait(clk,rst,finished); input clk; input rst; output finished;
reg finished;
reg [11:0] accum;
always @ (posedge clk or posedge rst) begin if(rst) begin accum = `WTIME) finished