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Reading O value

Hi Champs Its Isaac after long time,,,,,,,,,,,,,,I am having problem reading out values from SRAM in FPGA everytime I try to target SRAM I am getting

  1. The code is given below . The check node and variable node component's function is not mentioned here. Can any body pin point the problem....In state s6 I am reading out the values from FPGA. State s2 and s3 are not defined.

P_IO_FFS : process( CLK_2X, LOCKED ) begin if RISING_EDGE(CLK_2X) then if LOCKED = '1' then -- Outputs

-- LED_V3

Reply to
Isaac
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Oh, please.....

  • You have posted more than 400 lines of code.
  • The code contains no useful comments whatever.
  • Most of the signal names are incomprehensible.
  • All the state names are meaningless.
  • Many of the process sensitivity lists contain signals that they do not need.

Kindly put in the effort to isolate the problem more carefully. As part of that process, you should document your code. This documentation will help you in understanding what's going on for yourself.

If you still have a problem after you have done this, then at least you will be able to post something manageable and there is some chance that someone will try to help you.

-- Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

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Reply to
Jonathan Bromley

Jonathan, you left out a few:

  • processes without names/labels
  • long 'if/elsif' statements where 'case' is more appropriate
  • 'Std_Logic_Arith' used instead of 'Numeric_Std'
  • and finally instead of (#note 1)

This has to be the worst example of bad coding style that I've come across in a long time - LOL

#note 1 people who use tabs in source code should be hung drawn and quartered!.............. IMHO ;-)

--

Regards,

         Brent Hayhoe.

Aftonroy Limited
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Reply to
Brent Hayhoe

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