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reading files in vhdl

hi guys,

im having some trouble with reading from a file, actually the thing is the opening part. the problem is that i "dont" know the name of the file to read before compiling, that is because i've a "configuration" file where i give commands, one of them being the name of the "input" file.

i know i could use a function, but that only works when i've a small amount of data to read, cause otherwise, storing a HUGE array slows down the simulation, without saying that modelsim tells me that i has not enough memory and will start paging to disk and after a while it says that i got completely out of memory.

Simulation works perfect if i read one line (of the input file) at the time, but that means that the filename has to be written on the code (at least that's how i've been doing, by using ' file fp : TEXT is in "input.dat"; ')

now i need to open an arbitrary file, so i tried "file_open(fp, filenameString, READ_MODE);" the problem is that somehow it doesnt work, as it seems that if i open the file in one process (i have to open the file just once and read it till the end of the file at every rising_edge(clk), so that's two processes). It doesnt work cause it seems that the file is "closed" outside the process it was opened (i think i even read about that issue).

Also i cant find "file_open" declaration.

i also tried with a process like this: (im at home now, so i dont have the real sources, but i cant sleep so im writing to ask for help :) please)

process begin

if (filenameString /= nothing) then file_open(fp, filenameString, READ_MODE);

while (not endfile(fp)) loop wait until rising_edge(clk); read(fp, data); etc, etc end loop; file_close(fp); end if; end process;

that didnt work either, im not sure if it was because of the file_open part (i also did a check on the opening, it was succesful) or because the process get in an infinite loop, modelsim just stop responding (i think that endfile might return false if the file is not open, giving rise to the infinite loop, but the loop would at least be "waiting" for "clk" and it would actually read the data, but that doesnt happen). The file might get closed once "out" the process (like when another process gets executed) or something, i have no clue...

do any of you knows or have faced already this kind of situation? namely, reading a file whose name's specified after compilation (by another file) line by line (that is, not using a function to read a whole chunk of data and storing it in an array)

any comments will be appreciated, thanks

Paris

Reply to
paris
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Paris, None of your solutions are that far away fronm working.

You could use a procedure and never exit. Pass out one set of data values on every clock.

I am guessing that your file handle declaration is in the process and not the architecture. If the file handle declaration were in the architecture, I suspect that this would work. With your file handle declaration in a process, only the process that declares the file handle can see it.

It is built into the language.

else wait ;

This can work too, however, when filenameString = nothing, then the process goes into an infinite loop. If filenameString = nothing means do nothing forever, add an else branch with a wait statement in it as shown above.

Cheers, Jim

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
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Reply to
Jim Lewis

If you need to open an arbitrary file (like I often want to do), define it as a generic, with a default value. When you call the simulator (I've worked with Modelsim doing this), provide the generic as part of the call. E.g., vsim tb_config -ggeneric1=generic1value ... (other options.)

Then you can set up a script (or batch file) with whatever value you need for the generic-- or just manually type in every time you run it.

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Reply to
jtw

Hi, I used to do some thing similar, but then I figured out yet another easier way (atleast I find so). I refernce to a file named say "image_data.txt" inside my TB. Using a script around my simulator, I use UNIX links to simulate multiple images, infact you could do some thing like:

ln -s image_0.txt image_data.txt run # End of 1 sim with image_0 reset rm -f image_data.txt ln -s image_1.txt image_data.txt run # Second simulation with image 1!!

I did this using NCSIM - FYI.

HTH, Ajeetha,

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Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.

Reply to
Ajeetha Kumari

ENTITY EX_TOP IS generic ( outfilep_string : string :="results/CDAC_OUT.txt"; inpfilen_string : string :="data/CDAC_IN.txt" ); PORT( AVDD : IN real; AVDD_REF : IN real; AVSS : IN real; AVSS_REF : IN real; --input port list CDAC_OUTN : OUT real:= 0.0; CDAC_OUTP : OUT real:= 0.0 ); end;

The idea is to make the file as generic(here i have a default value for the files). Then during instantiation you can change the name of the file as per your requirement. By this the idea is to have multiple testcases which actually feed different input data and dump out different output files. I hope this helps

Best Regards, Sajan.

Reply to
Sajan

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