Re: User Core OPB Problem (EDK3.2)

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

The ssp0 core has a mir interface within. You need to assign the
addresses for
the mir registers. I.E:

BEGIN opb_core_ssp0
  PARAMETER INSTANCE = opb_core_ssp0_1
  PARAMETER HW_VER = 1.00.b
  PARAMETER c_BASEADDR = 0x21000000
  PARAMETER c_HIGHADDR = 0x210000ff
  PARAMETER c_mir_BASEADDR = 0x21000100
  PARAMETER c_mir_HIGHADDR = 0x210001ff
  PORT opb_clk = sys_clk
  PORT led = led
  BUS_INTERFACE SOPB = opb
END


Matthias Dyer wrote:
 > Hello,
 >
 > We are trying to implement an OPB slave user core as described in the
"User
 > Core Template Reference Guide" (Jan 2003). We are using the template
 > "opb_core_ssp0_v1_00_a". We have connected the user core to the OPB
Bus of a
 > Microblaze system (generated with Xilinx EDK3.2 SP1 tools). Now, having
 > this core as the only opb slave on the bus causes no problems. But
when we
 > connect other pre-build peripherials such as the "uart-lite", our core
 > interfers somehow with the other cores. In particular the uart output is
 > croped after 16 chars if our user core is present. This is a weird
behavior
 > since our core should have a well defined opb addres space and does only
 > read from the opb and does not write to it.
 >
 > This effect even occurs when we take an empty user core template!
 >
 > Have anyone had the same experience or can anyone help?
 >
 > Thanks a lot and best regards,
 >
 > Matthias
 >
 >




Site Timeline