I am just starting with VHDL and have been doing software for the last 20
>years. My project that I am trying to get working is part of a memory
>controller which will allow different processes to request access to the
>memory.
>
> The portion of the code that I posted works great when I do the Behavioral
> Model Simulation. When I do the post-Place & Route VHDL Model Simulation
> the first write cycle does not work. You can see that it processes
> through the states but the data out and address lines don't change as
> expected.
>
> I would appreciate any help with this problem. Hopefully it's just
> something stupid. That always makes me feel better.
>
> Joel
>
>
Joel, When I compiled the source to gates, and ran the simulation, I got a lot of timing violations.
In the testbench, how do you control the set up and hold of the inputs to the uut with respect to clk? (especially data_valid, rst, ack) Do you constrain tbe implementation with timing constraints from a UCF file?
-Newman