Re: TIG Constraint

Hi Martin,

TIG should work, if not, you could always try a MCP (multicycle path constraint) if you know how many times your data is sampled.

Anil

HDL

the

or

registers

per

nets

must.

formatting link
net

Reply to
Anil Khanna
Loading thread data ...

The constraint guide indicates that the TIG constraint can be used in HDL

> (Verilog in my current design). However, an attempt to use it produces

the

following error: > > ERROR:Xst:1582 - The constraint 'tig=' is not supported neither in BEGIN > MODEL/END section in the XCF file, nor in HDL code. > > I have not been able to find further information on this error message or > issue in the Xilinx site. Does anyone know if TIG is truly supported in > HDL? I'd hate to place it in the UCF file, to me it feels much more > approprite to have this constraint move with the HDL source. > > The form I'm using is: > > // synthesis attribute TIG of is ""; >

Using:

// synthesis attribute TIG of is "TRUE";

makes the error go away. Is there a way to verify that the net is be Set user-defined property "TIG = TRUE" for signal .

Being that the constraints guide does not list "TRUE" as a valid value I'd like verification that the constraint is truly doing something useful.

Thanks,

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian
 Click to see the full signature
Reply to
Martin Euredjian

Sure, I could use multi-cycle in the UCF (or TIF, for that matter). For maintainability (and reusability) purposes I wanted to include these and other constraints with the HDL file.

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian
 Click to see the full signature
Reply to
Martin Euredjian

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.