Yes, everything I have read (which is not a lot) simply relies on the control path (the clock) to have a longer delay than the data path. So the data will always reach the next stage before the control saying the data is ready.
There is no way to determine when a circuit is metastable or not. Async circuits are not magic, they just depend on predictable delays, just like any other circuit. The design is different because there is no common clock so each circuit can run with its own delay. Since the next circuit will take the output when it is ready, there is no problem with synchronization.
One problem I do see is that if each stage has a different delay, then it can not accept a new input from the preceding stage until the output has been taken by the following stage. It seems in the end the async circuit will run no faster than the slowest stage, which is what the sync clocked circuit will do.
But I have not read about it much, so perhaps there is more to it than just this. But without design tools or any expectation of using it soon, there is not much incentive to spend much time reading up on it now.