Re: Thinking out loud about metastability

Yes, everything I have read (which is not a lot) simply relies on the control path (the clock) to have a longer delay than the data path. So the data will always reach the next stage before the control saying the data is ready.

There is no way to determine when a circuit is metastable or not. Async circuits are not magic, they just depend on predictable delays, just like any other circuit. The design is different because there is no common clock so each circuit can run with its own delay. Since the next circuit will take the output when it is ready, there is no problem with synchronization.

One problem I do see is that if each stage has a different delay, then it can not accept a new input from the preceding stage until the output has been taken by the following stage. It seems in the end the async circuit will run no faster than the slowest stage, which is what the sync clocked circuit will do.

But I have not read about it much, so perhaps there is more to it than just this. But without design tools or any expectation of using it soon, there is not much incentive to spend much time reading up on it now.

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Rick "rickman" Collins

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rickman
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Rick, the electron spin is +1/2 or -1/2, there is no in between state, it changes instantaneously (in one fundamental clock tick, ~10^-43 seconds).

Luiz Carlos

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Luiz Carlos

Silly question: I don't see why an ANALOG flip-flop couldn't determine that it is in the intermediate state at some fixed interval after the clock, and then force the flop one way or another. Of course, it might double-glitch in the meantime (flop goes up before logic forces it down), but it would make a flop with a fixed-maximum metastabel interval.

Of course, it seems like such a massive headache to do.

The trick with asynchronous logic is that the longest stage WHICH IS IN THE COMPUTATION is the critical path. EG, if 9 of the stages take

1 ns, and the last takes 2ns, but the last only affects 1/2 the data, with the asynchronous circuitry doing the shortcutting, it will be considerably faster than the synchronous one.

The problem is: You can automatically balance the pipelining (retiming) for a synchronous circuit, while asynchronous really playes havoc with the CAD flow and testing.

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Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
Reply to
Nicholas C. Weaver

DING DING DING

Nobody has been able to fix metastability yet. If you really have a fix, it's worth a Nobel Prize.

The usual problem with that sort of approach is that you get a runt pulse on the fix-it signal in cases that would have worked correctly without it.

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Hal Murray

Yes, but the point is it would fix the maximum metastability window, which is the key requirement, as "did the data come before or after the clock edge" is really an irrelevant question at the metastable capture point, you jsut want it to go to ONE or the other (not stick around and make up its mind a half clock cycle later), and possibly to tell you.

This isn't FIXING metastability, this is detecting and responding to it, changing an exponentially decaying bounds into a fixed bounds.

Of course, it seems like way too big a headache to bother with.

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Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
Reply to
Nicholas C. Weaver

But the measurement is not instantaneous. So the transistion could occur during a measurement. Result... inconclusive measurement which is what metastability is all about.

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Rick "rickman" Collins

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rickman

If you don't see the problem it is because you are not looking hard enough. The issue with metastability comes from trying to measure the state of a FF or other digital voltage. When a signal is at an intermediate value a measurement can be inconclusive. Your ANALOG FF can be just as inconclusive as the digital FF. Besides, the result is always digital (or more accurately, discreet instead of continuous).

You are suggesting that you add a third state to the measurement, but you get the same inconclusive measurement between the metastable state and either the one or the zero states. The result is that the output of your ANALOG FF would be indeterminate which could result in metastability in the next stage.

If I am not grasping your idea, then please provide more details.

Except that sync designs can do the same thing. A multiply accumulate typically takes twice as long as the other ops in a calculation. So they split it into two stages running at full speed. Or if only half the data needs the MAC, then they can do nothing since this will run at full speed.

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rickman

The flip flop core exists in one of THREE states: Vdd, Vss (the stable points) and Vms +/- epsilon (the metastable range, in between Vdd and Vss).

The analog circuitry in the flip flop measures the flip-flop state at Tdelay after the clock edge.

If it is within Vms +/- a large epsilon (that is, metastable at this point in time), the analog circuitry forces the flip-flop to Vss, and also signals that a metastable capture/correction was performed.

This may cause a spurrious transition (eg, the metastable state is measured, it goes high, and then the post-measurement kick drags it back down to Vss).

The promise of the asynchronous is that this can occur on a much finer grain, eg if all the ops are 1 ns, but the final one is either 1 or

1.5 ns.

Of couse, it has never really lived up to this promise, mostly because the handshaking overhead can be severe, as well as the other problems (CAD, testing).

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Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
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Nicholas C. Weaver

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The problem is that the analog circuitry that is trying to determine if the flip-flop is in a metastable state can itself go metastable if the flip-flop level is near Vms +/- epsilon.

Daniel Lang

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Daniel Lang

You are not accounting for the fact that the voltage is being measured by the analog circuit and it can not distinguish between the metastable state and the non-metastable states any better than the original FF could distinguish the two valid states. If the voltage is at the cusp of the metastable range, the analog circuit will have an invalid or indeterminate output and will not drive the FF to a valid state. In fact, it may drive the FF back toward a state with an even longer transistion time.

This is very circular. Each measurement has a range in which the measurement is indeterminate within a given amout of time. That is the nature of metastability. It is not just the state of the FF. The FF became metastable because it could not measure the input to be either a

1 or a 0. Trying to measure the state of the FF has the same problem, ad infinitum.
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rickman

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Reply to
Ray Andraka

It might be that you can change the shape of the probability vs. time curve, while keeping the area constant. That could reduce the probability of metastability lasting too long for a given clock rate.

I don't know the physics well enough to say. Also, it might be pretty expensive to do that.

-- glen

Reply to
Glen Herrmannsfeldt

If you could build a circuit with a "fixed bounds", that would solve the metastability problem and you would be a hero. (Just set your clock period to that fixed bounds.)

I put metastability in the same category as perpetual motion. I assume any proposal is wrong, even if I can't spot the problem right away. Best one I've ever heard of was a bicycle wheel that ran off changes in air pressure.

If you have a circuit that you think will work, please send me the schematic. There is a reasonable chance I (or somebody here) can find the bug in it. No promises. The thing I would look for is runt pulses.

The best non EE-geek example of metastability I have seen is rolling a ball over a speed bump. Left of the bump is 0. Right of it is 1. Give it a good shove and it goes over. Give it a gentle shove and it bounces back. For some speed, the ball will teeter on the top for a while, then fall off one side or the other.

The initial speed of the ball corresponds to meeting setup/hold times. If the system is continuous, there is some value in the middle that will cause troubles. Setup/hold times and ball speed both seem continuous to me.

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Hal Murray

(snip)

One thing that I still remember from the first discussions about metastability was that the sharper you make the peak, the smaller the chance of getting into the metastable state, but the longer it stays when you get there. I don't know if the analogy is quite right, but consider a very sharp speed bump. It will deform the ball as it goes over, such that it sticks more.

Not so long after that, I was taking a shower at a pool with a valve designed not to stay on. I managed to get it into the metastable (stay on) state, so that I could wash with both hands. (It worked just like the speed bump, where on top of the bump the valve was on.)

-- glen

Reply to
Glen Herrmannsfeldt

You just need to measure the spins to see the results. You can maintain they stable during this. To carry out the operations the spins interact and you don't need to measure them. But, if you imply a measure in the interaction process, so the measure is instantaneous.

Luiz Carlos

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Luiz Carlos

Followup to: By author: rickman In newsgroup: comp.arch.fpga

Well, actually it is. It might *affect* the spin (Heisenberg wins again) but unlike classical measurements there shouldn't be any ifs about the result.

There is a lot of things in the quantum world which is completely counterintuitive to everything we have learned. If you look at quantum teleportation, for example, you'd have to conclude information was conducted backwards in time...

This is of course, impossible.

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H. Peter Anvin

It is possible -- I did it once for a FF design for another company. It requires a separate, combinational output signal ("metastable flag-out"). But, of course, there's no way to use this to kick the FF circuit itself out of metastability. All previous comments about this being a no-fix are true.

The flag is generated by taking advantage of the fact that the latch going metastable has a cross-coupled gate with a known threshold point during metastability. A 2-input logic gate with a different threshold can detect that both inputs (ie, Q and Q-bar) are above (or below) it's own (different by design) threshold point.

Cheers, Ron Cline

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Ron Cline

Why can't you use this flag to generate another (delayed) clock to the same FF? It would continue to retrigger itself until it was in a stable state. If you ORed all of these flags together in a register you would have a data valid output.

Nothin like async logic to get your blood flowing!

Tom

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Tom Seim

by

This newly-created feedback loop would have a much longer metastable time-constant than had the original latch. Better to leave well enough alone, I think.

The flag wouldn't indicate a logic state (valid or not), only the presence of metastability. The logic state is indeterminant while the flag is active.

- Ron

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Ron Cline

And what happens to the output of this MS-detector gate if one of the voltages is right at the threshold of the gate? Is it possible that the output of the gate is at an intermediate voltage and is therefore indeterminate?

Once again the problem comes from the measurement. There is no knife that is sharp enough to split every hair known to man or nature.

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Rick "rickman" Collins

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rickman

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