There is skew even in dedicated clock lines. Because clock nets are dedicated for just for clock signals skew is much smaller and can (more easily) be accounted for in place and route. Most FPGA tools warn about gated clocks because then your skew is no longer well known parameter of global clock net but depends heavily on your design.
-- Keijo Länsikunnas
There is always *some* skew, but whatever it is, the FPGA manufacturer guarantees that if you use the dedicated clock network then you will never suffer from the skew-related race condition that we discussed.
When designing ASICs and custom ICs, you achieve the same result by using specialised clock tree insertion software.
-- Jonathan Bromley, Consultant
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