Re: the skew and race condition

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View

Quoted text here. Click to load it

There is skew even in dedicated clock lines. Because clock nets are
dedicated for just for clock signals skew is much smaller and can
(more easily) be accounted for in place and route. Most FPGA tools
warn about gated clocks because then your skew is no longer well known
parameter of global clock net but depends heavily on your design.


--
Keijo Lšnsikunnas

Re: the skew and race condition

Quoted text here. Click to load it

There is always *some* skew, but whatever it is, the FPGA
manufacturer guarantees that if you use the dedicated clock
network then you will never suffer from the skew-related
race condition that we discussed.

When designing ASICs and custom ICs, you achieve the same
result by using specialised clock tree insertion software.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
We've slightly trimmed the long signature. Click to see the full one.

Site Timeline