Re: The real history of computer architecture: the short form

The enormous throughput of GPU's, special-purpose processors like
>GRAPE, and speculation about PlayStation keep my interest in what >might be possible if you wanted to build a special-purpose compute >engine.

Special-purpose compute engines are unavoidably rather expensive;

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gives a couple of interesting directions to look in for the technology level that's actually close to affordable.

The second-biggest Spartan3 chip has 96 18x18->36 multipliers, which gives you eight 54x54 and a 72x72 to work with. A medium-sized XC2VP50 Virtex2 Pro has 232 of the 18x18 multipliers, and a pair of PPC440 CPUs -- and sixteen Hypertransport links -- but probably costs as much as a Madison 1300MHz/3MB (IE $2000 or so). But I don't know what speed you can clock that great array of multipliers at.

[note I've cross-posted this to comp.arch.fpga in case they know the speed and cost details off the top of their heads; the idea is to implement an array of double-precision FMA units on an FPGA, to see how they'd compare to the few much-faster-clocked FMAs on high-end CPUs. I don't know how exotic the Spartan3/4000 or the XC2VP50 are]

Tom

I've done some back-of-the-enveloping. It looks reasonable to make a vector procesor that is about 1/2 to 1/4 the throughput of the Earth Simulator vector processor in a large FPGA (eg, V2Pro), eg 8 lane, 8 FP MAC/cycle, but only ~250 MHz.

The interesting parts really come in not in the computation but in the communication: how do you do a low latency, high throughput, flexible network to connect a whole BUNCH of computing elements. This is where the FPGAs get interesting, with 3 Gbps SERDESes being standard and 10 Gbps SERDESes on the near-term horizon. With a cut-through routing, the latency per hop is fairly low (~20-30 cycles at the 3 GHz stream clock), so a network could be made that isn't full connectivity like a crossbar, but is rather fast and routed.