I'm a sysadmin looking at a problem that a designer is having with
> slow turn around times in Altera Quartus. The turn around time on a
> compile is about 1 hr on a AMD 1700+ with 1 gig of memory. Quartus
> version is 2.1 running on Win2K SP2.
Gosh. I wish I had a sysadmin. Any openings? :)
One hour is not bad for synthesis and place+route on a medium sized FPGA.
There is apparently a way to lock down the layout of certain blocks
> and/or do an incremental compile so that everything would not have to
> be re-synthesised but the designer says that it doesn't seem to work
> correctly.
I haven't even tried the "logic-lock" place+route locker because things change too much and I don't do that many place+routes.
You should turn on "smart-compile" to save the cache. Hard drives are cheap.
Any pointers would be greatly appreciated.
A simulation recompile and rerun only takes a few minutes. You might suggest the designer spend more time on the testbench and less in synthesis/place+route.
-- Mike Treseler