Re: speeding up quartus

I'm a sysadmin looking at a problem that a designer is having with

> slow turn around times in Altera Quartus. The turn around time on a > compile is about 1 hr on a AMD 1700+ with 1 gig of memory. Quartus > version is 2.1 running on Win2K SP2.

Gosh. I wish I had a sysadmin. Any openings? :)

One hour is not bad for synthesis and place+route on a medium sized FPGA.

There is apparently a way to lock down the layout of certain blocks > and/or do an incremental compile so that everything would not have to > be re-synthesised but the designer says that it doesn't seem to work > correctly.

I haven't even tried the "logic-lock" place+route locker because things change too much and I don't do that many place+routes.

You should turn on "smart-compile" to save the cache. Hard drives are cheap.

Any pointers would be greatly appreciated.

A simulation recompile and rerun only takes a few minutes. You might suggest the designer spend more time on the testbench and less in synthesis/place+route.

-- Mike Treseler

Reply to
Mike Treseler
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Off the subject but I have been really glad to see Altera's presence in this forum for the last few months.

For years it seemed that only Xilinx cared about their user community on here so its nice to see the support. Kudos to Paul, Subroto et al. (and continuing thanks to Austin, Peter et al from Xilinx)

Mike hit the nail on the head, most work should be done pre-synthesis. Of course the Altera product (or Xilinx) doesn't really lend itself to doing this by itself. I'd recommend Active HDL

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though others swear by ModelSim

You 'really' need a decent simulator to speed the overall design process.

Paul

unreasonable

fitter

past

lock

Reply to
Paul Baxter

Paul, The device is an EP20K, 1500EBC652-1X, the user said that he is using suggest upgrading to the latest version of Quartus II (version 3.0) as I

Reply to
Don S

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