Modelsim PE (with swift license) or modelsim SE is required to simulate.
Hi,
>
> I downloaded the 6.1i Update #1 in order to be able to generate the 1
> gigabit ethernet mac with coregen. It should be possible to simulate the
> generated ip. However, I'am not able to do so. After running the
> implement.bat file from a command line, I start modelsim XE (full
edition).
I navigate to the test/vhdl directory and run the command "do
> simulate_mti.do". Two warnings are generated and the simulator is being
very
very busy? It's very slow in generating the results in the wave window. Is
> this normal, or should the testbench be executed in "no time"? And what
> about the warnings that are generated??
>
> Modelsim output generated:
>
> # Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
> # -- Loading package standard
> # -- Loading package std_logic_1164
> # -- Loading package vital_timing
> # -- Loading package vcomponents
> # -- Loading package vital_primitives
> # -- Loading package textio
> # -- Loading package vpackage
> # -- Compiling entity netlist
> # -- Compiling architecture structure of netlist
> # -- Loading entity x_zero
> # -- Loading entity x_ff
> # -- Loading entity x_buf
> # -- Loading entity x_ibufds
> # -- Loading entity x_dcm
> # -- Loading entity x_ckbuf
> # -- Loading entity x_lut3
> # -- Loading entity x_one
> # -- Loading entity x_lut4
> # -- Loading entity x_lut2
> # -- Loading entity x_mux2
> # -- Loading entity x_sff
> # -- Loading entity x_srlc16e
> # -- Loading entity x_xor2
> # -- Loading entity x_and2
> # WARNING[1]: routed.vhd(38389): No default binding for component: "x_gt".
> (No entity named "x_gt" was found)
> # -- Loading entity x_or2
> # -- Loading entity x_tri
> # -- Loading entity x_inv
> # -- Loading package vital_timing
> # -- Loading entity x_roc
> # -- Loading entity x_toc
> # Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
> # -- Loading package standard
> # -- Compiling entity testbench
> # -- Loading package std_logic_1164
> # -- Loading package numeric_std
> # -- Compiling architecture behav of testbench
> # -- Loading package vital_timing
> # -- Loading package vcomponents
> # -- Loading package vital_primitives
> # -- Loading package textio
> # -- Loading package vpackage
> # -- Loading entity netlist
> # vsim -t ps work.testbench
> # Loading C:/Modeltech_xe/win32xoem/../std.standard
> # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body)
> # Loading C:/Modeltech_xe/win32xoem/../ieee.numeric_std(body)
> # Loading C:/Modeltech_xe/win32xoem/../std.textio(body)
> # Loading C:/Modeltech_xe/win32xoem/../vital2000.vital_timing(body)
> # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.vcomponents
> # Loading C:/Modeltech_xe/win32xoem/../vital2000.vital_primitives(body)
> # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.vpackage(body)
> # Loading work.testbench(behav)
> # Loading C:/Modeltech_xe/win32xoem/../ieee.vital_timing(body)
> # Loading work.netlist(structure)
> # Loading
C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_zero(x_zero_v)
# Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_ff(x_ff_v)
> # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_buf(x_buf_v)
> # Loading
> C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_ibufds(x_ibufds_v)
> # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_dcm(x_dcm_v)
> # Loading
>
C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.dcm_clock_divide_by_2(dcm_c
lock_divide_by_2_v)
> # Loading
>
C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.dcm_maximum_period_check(dc
m_maximum_period_check_v)
> # Loading
>
C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.dcm_clock_lost(dcm_clock_lo
st_v)
> # Loading
> C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_ckbuf(x_ckbuf_v)
> # Loading
C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_lut3(x_lut3_v)
# Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_one(x_one_v)
> # Loading
C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_lut4(x_lut4_v)
# Loading
C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_lut2(x_lut2_v)
# Loading
C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_mux2(x_mux2_v)
# Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_sff(x_sff_v)
> # Loading
> C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_srlc16e(x_srlc16e_v)
> # Loading
C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_xor2(x_xor2_v)
# Loading
C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_and2(x_and2_v)
# ** Warning: (vsim-3473) Component
> 'gmac_core_bu2_u0_gpcs_pma_inst_mgt_mgt_gt' is not bound.
> # Time: 0 ps Iteration: 0 Region: /testbench/dut File: routed.vhd
> # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_or2(x_or2_v)
> # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_tri(x_tri_v)
> # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_inv(x_inv_v)
> # Loading C:/Modeltech_xe/win32xoem/../ieee.vital_primitives(body)
> # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_roc(x_roc_v)
> # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_toc(x_toc_v)
> # WARNING: No extended dataflow License exists
> # .source .process .signals .variables .dataflow .list .wave
> # ** Note: Resetting core...
> #
> # Time: 0 ps Iteration: 0 Instance: /testbench
> # ** Note: Timing checks are valid
> #
> # Time: 700 ns Iteration: 0 Instance: /testbench
> # ** Note: Disabling Auto-Negotiation in PCS sublayer....
> #
> # Time: 700 ns Iteration: 0 Instance: /testbench
> # ** Note: Transmitting four frames...
> #
> # Time: 27600 ns Iteration: 1 Instance: /testbench
>
> TIA,
> Frank
>
>