Re: Signal within block

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Perhaps you mean a top architecture with 12 instances of some entity.

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Each instance has a unique label:

    my_entity_1 : entity work.my_entity
       port map (reset  => reset_sig,  -- [in]
                 clk    => clk_sig,    -- [in]
                 i      => i_1_sig,    -- [in]
                 o      => o_1_sig);   -- [out]

    my_entity_12 : entity work.my_entity
       port map (reset  => reset_sig,  -- [in]
                 clk    => clk_sig,    -- [in]
                 i      => i_12_sig,   -- [in]
                 o      => o_12_sig);  -- [out]

The signal associated with an instance port is whatever
you define it to be in the port map.
I think of this as "wiring up" the instances.
These "wire" signals must be declared between
the IS and BEGIN of the top architecture.
It can be a different signal for each instance if you like.

 > Is there is any way to access these Signal in VHDL?

These signals are accessible anywhere in the top architecture.

  -- Mike Treseler




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