Re: Reusing CCLK line after configuration for Spartan-II

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 Exactly, this is what I was referring to. Sorry if it was not clear.
I want to share the same CCLK line for another purpose after the FPGA
has been configured. This will be a toggling 5V signal. Will the
(sleeping) CCLK will have any concerns with that?

 Thanks again. Regards.

Re: Reusing CCLK line after configuration for Spartan-II

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Here is some official documentation - look at Answer # 10046 in Xilinx's
Answer Database.  If this applies to Virtex, I believe it should to the
Spartan II as well, since it is a derivative device.



Re: Reusing CCLK line after configuration for Spartan-II
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 Jim, thank you very much. I had missed that answer (only looked up
for Spartan). I think that will do.

 Regards!

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