Right click on the block you created. You can use use the Create Design File From Selected Block. to generate a lower level Schematic file (bdf), VHDL file (vhd), Verilog File (v) or AHDL (tdf) file for the selected Block. These generated files will contain the I/O definitions that were defined by the block. You can then open the generated file and enter the rest of the design.
For example my schematic had a block called block_name with 4 ports. I right clicked on the block and used the Create Design File From Selected Block command to generate the file block_name.vhd file. The contents of the generated block_name.vhd is as follows:
.....Copyright text
-- Generated by Quartus II Version 3.0 (Build Internal Build 225 08/11/2003)
LIBRARY ieee; USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY block_name IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( a : IN STD_LOGIC; b : IN STD_LOGIC_VECTOR(2 downto 0); c : OUT STD_LOGIC; d : OUT STD_LOGIC_VECTOR(3 downto 0) ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END block_name;
-- Architecture Body
ARCHITECTURE block_name_architecture OF block_name IS
BEGIN
-- Enter your logic here END block_name_architecture;
Hope this helps.
- Subroto Datta Altera Corp.