Hi Martin,
Finally got an answer for you on this. This is indeed a bug in the Quartus extractors; your test case was helpful in tracking down this problem. Apparently the extractor guys had been looking for a problem like this but hadn't been able to isolate it until now. A Software Problem Report has been filed and this should be addressed in a future version of Quartus or a service pack.
Regards,
Paul Leventis Altera Corp.
Since Leonardo is not longer available from Altera I'm trying to use
Quartus
for synthesis. But I get a different output with Quartus. I tracked the
> problem down and now my qustion is: Is it a bug or sloopy written VHDL?
>
> The problem is setting output to tristate. See following VHDL code: I
asumed
that it is ok when the databus (d) is set to 'Z' in state 'idl' and this
> will not change when changing state to 'rd1'. This was ok with Leonardo.
But
with Quartus I have to set d to 'Z' again in every state. What is the
> correct VHDL code?
>
> Martin
>
> process(clk, reset, din, mem_wr_addr, mem_rd, mem_wr)
> begin
> if (reset='1') then
> state a d ....
> elsif rising_edge(clk) then
> case state is
> when idl =>
> a d
> if (mem_rd='1') then
> a nram_cs ram_access i := ram_cnt;
> nrd state elsif (mem_wr='1') then
> ...
> when rd1 =>
> d NOT in Leonardo
> i := i-1;
> if (i=0) then
> state mem_din(7 downto 0) a(1 downto 0) i := ram_cnt;
> end if;
>
> when rd2 =>
> d i := i-1;
> if (i=0) then
> ...
>
> --------------------------------------------------------
> JOP - a Java Processor core for FPGAs now
> on Cyclone:
formatting link
>
>