> Hello,
>> How are typical CPLD input muxen build up?
>
> (For other posters, a CPLD is a "complex programmable logic device". It
> is a bit like a simple FPGA - there is no fixed dividing line between
> them, but CPLD's tend to be built from a fairly small number of fairly
> complex "macrocells" containing a flip-flop and a set of AND/OR trees
> for logic operations, while FPGA's tend to have a large number of much
> simpler cells and use lookup tables for logic.)
>
>>
>> I was looking at the ATMEL .jed files and
>> their input muxen seem to be a series of sparse, one-
>> hot encoded bitfields with fewer bits
>> than inputs in total. So now I am wondering:
>> How are they distributed?
>> Just the name of the permutation problem might help, or
>> some other relevant search terms.
>>
>
> You are unlikely to be able to make sense of the programming file for
> even the simplest of PLD. It is not information that is published by
> the manufacturers, making it almost impossible to figure out which bits
> are used for the routing, the AND/OR tables, and other features. But it
Their .jed files have comments... In this case I know which is which. guessing the and-matrix assignment is trivial(done from the input equations). The meaning of the MC fuses can be found by trial&error, I believe. the mux feeding those input lines is different... there's 40 lines coming into the and array from the outside(80 counting both inv and noninv ones). +16 local loopbacks(not muxed)... but the widths of the 40 muxes are not sufficiently large to do arbitrary selections from the inputs. as far as I can tell from their docs and .jed their devices have dev: 1502 1504 1508 input lines: 68 132 260 mux width: 5 8 27 (40 muxes in their input switch) [...]