Re: Pulse stretching

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The decision on what works "better" is dependent on why you need to stretch
the pulse.

If you need a signal that's big enough to be sensed in a different clock
domain, an "acknowledge" can be brought back to the first time domain to
shut the pulse back off.  This assumes that two pulses won't be close enough
to interfere.

If we stick with your original approach, rather than using the |stretcher in
your construct below, I'd turn longer_pulse into a set/reset flop that's
started with the single_clock_pulse and ended with the stretcher_sr[2], i.e.

  longer_pulse <= longer_pulse ? ~stretcher_sr[2] : single_clock_pulse;

Two very-close events would only produce one pulse with this arrangement
rather than the extension that you'd get with the wide or.  The only reason
to use the alternative arrangement is to get the shift register in an SRL
for a Xilinx device or to reduce the width of the logic for a wider pulse
than what you're using.



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Re: Pulse stretching

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enough

Right.  I've used this approach in some modules, like both sides of a FIFO
operating across clock-domain boundaries.  I had to resort to stretching
when the signal in question had to go to multiple desitinations and it
didn't seem practical to generate and maintain different pulse <-> ack
channels.  My personal bias is that it made everything seems a bit messy.

My general approach to clock domain crossing has been to stretch the pulse
(if necessary) to guarantee that it will span several of the receiver's
clock cycles; re-sample with at least four F/F's and edge-detect.  So far,
so good.

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reason

A single SRL sounds good to me.

Thanks,


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Martin Euredjian

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Re: Pulse stretching
You might want to look at an article I wrote some time ago:
"Moving data across asynchronous clock boundaries".
You find it among the TechXclusives.
http://support.xilinx.com/xlnx/xweb/xil_tx_home.jsp

Peter Alfke, Xilinx
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Martin Euredjian wrote:
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