Matt, Generally speaking, this kind of problem indicates that the device did not correctly receive the preamble to the configuration bitstream, and therefore did not start to process the data. This explains why nSTATUS doesn't go low; the device has not yet started to look at the CRC for each frame of data.
The #1 reason for configuration issues is signal integrity issues on the DCLK signal. Even though it is running pretty slow, it's still a clock and therefore sensitive to ringing. The ringing causes double-clocking on the FPGA, so it sees a given bit twice. To diagnose this, probe at the DCLK on the Cyclone device as close as you can and observe the signal. If probing it makes it work, then it's signal integrity as the capacitance of the probe is damping the ringing. Or maybe you'll see ringing. Putting in a series termination at the microprocessor, or a parallel termination at the Cyclone, will generally solve this problem.
Other things to check:
- signal integrity on the DATA signal. Usually not a problem, but possible.
- When you send the data to the Cyclone, make sure you send each byte LSB first.
One of these is most likely the problem.
Sincerely, Greg Steinke snipped-for-privacy@altera.com Altera Corporation