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Re: Open Source GPGPU core

I tried building your toolchain on both a 32 and 64 bit amd Ubuntu 14.10 system and get:

Linking CXX shared library ../../../lib/liblldb.so Python script sym-linking LLDB Python API Program error: Invalid parameters entered, -h for help. You entered: ['--buildConfig=', '--srcRoot=/home/johne/Desktop/Nyuzi/NyuziToolchain/tools/lldb', '--targetDir=/home/johne/Desktop/Nyuzi/NyuziToolchain/build/tools/lldb/source/../scripts', '--cfgBldDir=/home/johne/Desktop/Nyuzi/NyuziToolchain/build/tools/lldb/source/../scripts', '--prefix=/home/johne/Desktop/Nyuzi/NyuziToolchain/build', '--cmakeBuildConfiguration=.', '-m'] (-1)

tools/lldb/source/CMakeFiles/liblldb.dir/build.make:282: recipe for target 'lib/liblldb.so.3.7.0' failed

make[2]: *** [lib/liblldb.so.3.7.0] Error 255 CMakeFiles/Makefile2:12189: recipe for target 'tools/lldb/source/CMakeFiles/liblldb.dir/all' failed

make[1]: *** [tools/lldb/source/CMakeFiles/liblldb.dir/all] Error 2 Makefile:133: recipe for target 'all' failed make: *** [all] Error 2 johne@ouabache:~/Desktop/Nyuzi/NyuziToolchain/build$

John Eaton

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jt_eaton
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It looks like LLDB was not building correctly when the build type wasn't set (I normally build with Debug). I pushed a change to the cmake files that should address this. Let me know if that fixes it.

Thanks

--Jeff

Reply to
jeffbush001

set (I normally build with Debug). I pushed a change to the cmake files that should address this. Let me know if that fixes it.

That fixed it. Ran all the tests and got the picture in the frame buffer.

Do any of the tests run verilator to create a vcd dump file?

John Eaton

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jt_eaton

Ok I found it. Are all of your tests all using the same vcd dump file?

John Eaton

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jt_eaton

Great!

Yep. All of the cosimulation tests run in Verilator. The compiler tests c an be made to run in verilator by defining USE_VERILATOR=1 in the shell e nvironment. The render tests have a target 'verirun' that will run them in Verilator (there are READMEs in those directories with more details)

VCD dumps aren't produced by default, but can be enabled by modifying the m akefile in the rtl/ directory, uncommenting the line:

VERILATOR_OPTIONS=--trace --trace-structs

And rebuilding. A file 'trace.vcd' will be written in the same directory. T he output files get big fast for non-trivial tests. :)

Reply to
jeffbush001

How many gates does it take once synthesized? Are there any Altera- specific constructs in code or is it portable?

Reply to
Aleksandar Kuktin

The default configuration with 1 core takes around 70k LEs on Altera. Almos t all of the design is generic behavioral RTL without custom megafunctions. The exception are SRAM and FIFO modules, which generally need to be tweak ed for the specific target to infer properly.

Reply to
jeffbush001

Okay, so this sounds fun. Gonna clone it and see what's inside. :)

Reply to
Aleksandar Kuktin

Amazing project :)))

Reply to
Antonio V

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