Re: NgdBuild:477 - clock net xx has non-clock connections

Thomas,

Ngdbuild is warning that what it thinks is a clock (but is actually a reset) is not connected to clock pins of various components. When I have seen this warning it was usually as a result of having some non clock nets driven by a clock buffer, i.e. a bufg.

Colm.

Thomas wrote:

I get the following warning: > > WARNING:NgdBuild:477 - clock net 'resetlogic_local_reset' has non-clock > connections. These problematic connections include: pin clr on block > resetlogic_resettimer_3 with type FDCE, pin pre on block > resetlogic_resettimer_0 with type FDPE, pin pre on block > resetlogic_logicreset with type FDPE, pin pre on block > resetlogic_resettimer_1 with type FDPE, pin pre on block > resetlogic_cpureset > with type FDPE, pin pre on block resetlogic_resettimer0_1 with type > FDPE, pin > pre on block resetlogic_resettimer0_0 with type FDPE, pin pre on block > resetlogic_resettimer_2 with type FDPE, pin pre on block > resetlogic_resettimer_4 with type FDPE > > ... that signal is a reset signal that stays low for a few clocks then goes > high. What does this message mean? > the xilinx doc, is (once again | as usual | as expected ) useless at > describing what it is.
Reply to
Colm Clancy
Loading thread data ...

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.