Rudi,
>
> The Architecture Wizard should generate a component with a
> CLKIN_IBUFG_OUT output port (if the 100 MHz clock is coming from a
> pad). Send that signal from the dcm60 into the CLKIN_IN port of the
> dcm75. Also, for your dcm75, in the Architecture Wizard, specify that
> the clk is coming from an internal source. This will prevent an IBUFG
> from being inserted in the dcm75 file. This worked for me.
>
> Code snippet below:
>
> Inst_dcm60: dcm60 PORT MAP(
> CLKIN_IN => clk100,
> LOCKED_OUT => open,
> CLKFX_OUT => clk60,
> CLKIN_IBUFG_OUT => clk100_ibufg_out,
> CLK0_OUT => open
> );
>
> Inst_dcm75: dcm75 PORT MAP(
> CLKIN_IN => clk100_ibufg_out,
> LOCKED_OUT => open,
> CLKFX_OUT => clk75,
> CLK0_OUT => open
> );
>
> If you need the rest of the code, I can send it to you.
>
> Regards,
> Ben
Hi Ben,
yes I have tried that as well, and yes it does work, except the timing between the 60 and 75 MHz clocks can not be separated (at least thats what it seems to me).
It creates a dependency between the clocks (I think). I meet the 60 MHZ timing but the 75MHz timing is off by a factor of 2 ! (I meet all timing if I use separate clock inputs for the DCMs.)
How do you constrain the outputs of the DCMs in your UCF file ?
Thanks ! rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores ->
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