Hi Lan,
you should not need to do any of this. After opening a V2PDK shell (Windows) or sourcing v2pro_setup (Solaris) change into your project directory. After editing flow.cfg (if necessary) type "make synth". Synplify will open (if you didn't chose to add -batch in flow.cfg) and you can synthesize the design. After leaving synplify type "make fpga" to start the implementation followed by "make bit" to generate the bitstream.
- Peter
Lan Nguyen wrote:
Hi,
>
> I did the synthesis with Synplify 7.3 and got the output "top.edif".
> Then I used "edif2ngd" to convert "top.edif" to "top.ngo". This is
> where I got the problem. The "top.ngo" was not properly produced, so
> the program stopped and popped up the error:
>
> "ERROR:XdmHelpers:828: File "top.ngo" is not in NGD or XDB format".
>
> I could not figure out what the problem is.
>
> Any help would be very appreciated.
>
> Lan
>
> > Lan,
> >
> > while XST is not supported for the ml300_embedded_* design shipping with
ML300/V2PDK 1.5 it
> will work with the Verilog version but not work with VHDL. However, you will
have to remove
> some peripherals from the system by modifying flow.cfg and changing the
yes/no table at the
> end of the file.
> >
> > The default setup for the ml300_embedded_verilog design is the one that is
part of the
> ML300 ACE files, ie. Linux will boot even if there are devices like AC97 and
others that
> are not directly supported by Linux.
> >
> > flow.cfg is the central file for all configurations, tools, SW, peripherals,
etc.
>
> > - Peter
> >
> >
> > Lan Nguyen wrote:
> >
> > > Hi Peter,
> > >
> > > I've got the Developer's Kit V2PDK VP4. I wanted to run the reference
> > > designs and test the results via the serial port. I tried and got
> > > nothing in the HyperTerminal.
> > >
> > > Does XST work for the synthesis ? If so, what modifications do I have
> > > to make ?
> > >
> > > (I was told that the only way is to get Synplify synthesis tool)
> > >
> > > Thanks
> > >
> > > Lan
> > >
> > > > Yes, it does. The reference design actually comes with the MLD
(Microprocessor
> > > Library Definition) technology that allows you to automatically generate
a BSP
> > > for Linux consisting of Xilinx layer 0 and 1 drivers according to the
hardware
> > > definition (MHS). When you generate the libraries from the
system_linux.xmp
> > > project file you will get this BSP.
> > > >
> > > > The BSP will also contain necessary patches to the Linux kernel to make
the
> > > design work with MontaVista Linux 3.0 (FYI: the only thing that needs to
be
> > > patched is the code for the Xilinx interrupt driver since the interrupt
> > > > controller from V2PDK and EDK are different)
> > > >
> > > > - Peter
> > > >
> > > >
> > > > tk wrote:
> > > >
> > > > > Hi Peter,
> > > > >
> > > > > I would like to ask if the reference design support
> > > > > MontaVista Linux Pro 3.0 ?
> > > > >
> > > > > Thanks very much!
> > > > >
> > > > > tk
> > > > >
> > > > > Peter Ryser wrote:
> > > > >
> > > > > > Antti,
> > > > > >
> > > > > > the EDK reference design for ML300 contains
> > > > > > - 1 PPC 405
> > > > > > - 1 PLB DDR
> > > > > > - 1 PLB bus with arbiter
> > > > > > - 1 PLB2OPB bridge
> > > > > > - 1 PLB BRAM controller with 32 KB BRAM attached
> > > > > > - 1 OPB Uart
> > > > > > - 2 OPB GPIO
> > > > > > - 1 OPB 10/100 Ethernet (interrupt driven)
> > > > > > - 1 OPB IIC
> > > > > > - 1 OPB System ACE CF
> > > > > >
> > > > > > There is no touchscreen, PS/2, TFT, parallel port and AC97. Adding
these
> > > > > peripherals to the design is planned for a later release that will
most
> > > > > likely happen towards the end of the year.
> > > > > >
> > > > > > There is some documentation in the zip file that lists the
peripherals and
> > > > > explains the design.
> > > > > > Again, please contact your Xilinx FAE if you would like to get
access to
> > > > > this design.
> > > > > >
> > > > > > Thanks,
> > > > > > - Peter
> > > > > >
> > > > > >
> > > > > >
> > > > > > Antti Lukats wrote:
> > > > > >
> > > > > >> >
> > > > > >> > If you want to work with EDK please contact your FAE and ask him
to get
> > > > >> > you access to the EDK reference design for ML300. He will be able
to
> > > > >> > get you access to the design.
> > > > > >>
> > > > > >> Hi Peter,
> > > > > >>
> > > > > >> when we received the EDK + DDR project, I also asked to be notified
> > > > > >> when a better EDK ref. design will be available, and so far have not
> > > > > >> got any more info, could you please enlight us what additional cores
> > > > > >> are available in the EDK ref. design you mentioned?
> > > > > >>
> > > > > >> ASFAIK TFT and Touchscreen are not implemented (or hopefully are
now?)
> > > > >> I have still having trouble to get EDK to work correctly using the
> > > > > >> obsoleted TFT ref. design - eg. display is looking in stripes 8
pixels
> > > > >> missing after 8 ok pixels - if the problem is fixed and ref design
> > > > > >> availabl would be greate.
> > > > > >>
> > > > > >> antti