Hi,
>
> Is it possible to simulate Metastability? Not in the functional
> simulation. But in Gate level Netlist simulation.
>
> Regards,
> Muthu
Many decades ago, an elder EE would recant his lab story to show the youngens about metastability (who of course didna believe such fairy tales). He had a bench setup with an old 4000 series FF (I mean RCA
70's cosmos family). The latch would be driven by a D/A converter to some middle value and let go, see how long it would take to settle one way or the other. Point was to get it automatically to stay indeterminite for the longest possible time. Can't remember how long that was, probably in ms range (maybe even secs) but it definitely showed a FF being less than perfect.At the time we were working with NMOS so alot of idiot type circuit design was floating around (multiple Vt drops, neg bootstrapping etc) that would have produced pretty nasty chips had not CMOS come along.
If you want to do that experiment today, you could work on a DRAM controller and pull the refresh cycle out till the data is not quite sensed right. Its the same deal inside, a perfectly balanced latch with din (decaying) and 1/2 din ref on other side.
regards
johnjakson_usa_com