> Hi Jean,
> >
> > I know that the frequency
> > synthesis shows is only estimated.
> > The real problem is that I have
> > a .xcf file in which I have
> > defined clk freq constraint, and
> > after PAR everything looks OK. ISE
> > even reports that timing
> > constraints are met. Later, when I
> > run gate level simulation, using
> > frequency which is close to the
> > maximal, I do not get good
> > results.
> >
> > BR,
> > Marija
> >
>
> Something similar just happened to me, and I believe I have fixed it
> (I'm currently into the second day of error-free post-PAR timing
> simulation). First of all, are you simulating using the SDF
> back-annotations in your simulations? If so, your simulator should tell
> you exactly where (if) any timing errors are happening. In my case,
> when I first did the timing simulation, I was getting multiple
> violations on the input flip-flops to my module (I have combinational
> logic in between my inputs and the first synchronous elements) despite
> having met all timing constraints in PAR. The problem seems to have
> been that ISE assumed my signals were coming from pads instead of
> another synchronous module, and I assume this changed its timing
> analysis. By including the "wrapper" synchronous elements and logic in
> my synthesis (which were already in my simulation), ISE seems to have
> correctly routed to respect my timing. At the very least, Modelsim
> hasn't given me any timing violations (cross fingers, knock wood ;).
> Hope this helps,
Another thing that happens in simulation is rounding errors. If the simulation is getting very near the maximum frequency, you may need to set the resolution to 1 ps if you haven't already done so. This is also necessary to get proper synthesis of DCM's and DLL's in Xilinx parts.