Hey guys, I'd recommend that splitting up your design into smaller projects is not the way to proceed, IMHO. You are just going to complicate your design and make it more difficult to simulate.
How much memory does your PC have? What's the processor? Is the hard disk working a lot during compilation? Check the memory usage using the Task Manager: see if the machine is running out of RAM and paging to hard disk. If so, you should buy some more RAM: RAM is cheap, far cheaper than messing around with your project to get it to compile in a smaller memory space. Paging to hard disk will slow down compilation vastly (perhaps by a factor of 10 or more).
You should alsi install DK2.0 SP1 and PDK 2.0. PDK 2.0 has a new standard library with more efficient implementations (in terms of compilation time) of the useful macros.
Don't use the netlist simulator: this is old and has not been updated for a while. I think it is provided by Celoxica merely for backwards compatibility or for long-term users. The new simulator simulates a lot faster and is much more stable. Also, the netlist simulator cannot simulate multiple projects at once any more than the new simulator can.
Make sure you have the latest version of the Xilinx tools with the latest service packs.
Things you can look for are: heavy use of recursive macros. These should be avoided as they take a lot of time and memory to compile. Read the Celoxica Knowledge Base
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for tips on optimising your design: there is plenty of useful information there. Sometimes optimisations that produce more efficient code can also bring down the compilation time.
Good designing
Noel
"P. Prasad" wrote in
> message
> news: snipped-for-privacy@chandra.cse.iitb.ac.in...
> > Hi,
> > I am working on a HANDELC project on Xilinx FPGA(RC1000
> board) and using Celoxica's DK1 environment. I have some
> doubts regarding HANDELC. I am new to HANDELC and FPGA.
> >
> >
> > The Problem
> > -----------
> >
> > As the project is getting bigger and bigger, the
> compilation(synthesis into EDIF) time is taking many hours.
> So the goal is to reduce the compilation time.
> >
>
> My experience of this is that people don't think enough
> about hardware.
> For instance, if you divide by 2^12, I have seen code where
> people write
>
> A = B /4096;
>
> This will result in HandelC attempting to synthesise a large
> divider.
> This is a) very slow in hardware b) very slow to compile.
>
> So my first suggestion is to look through your code for
> "sillies" like this.
> You can get big clues by getting the timing and area reports
> from DK1 and
> correlating them with the code you've written.
>
> (By the way, the above line should be
>
> A = B
> which essentially synthesises to some wires!)
>
> So step one is to check the code for sensible "hardware"
> style coding.
>
>
> > The approach which I tried to use was to break up the
> program into smaller parts, compile these into separate
> EDIFs and hook them into the main HANDELC program using
> interfaces(ports). So the parts of the program which have
> already been synthesized into EDIF do not take any time at
> all thus saving lot of time.
> >
> > But I am doing some mistake in my code and I am clueless
> to what is wrong. Actually I feel that I need to synchronise
> the EDIF component with the main HANDELC program but don't
> know how ( maybe use interfaces properly???). I have given
> below the detailed description of the things I tried.
>
> You approach makes sense. Remember that you need to create
> separate
> mains (i.e. separate projects) in DK1 to create separate
> EDIF netlists.
>
> Secondly, when you combine everything, you cannot simulate
> it in
> the C simulator - you would have to simulate it in the
> netlist simulator.
>
> I guess in your example below, you are talking about "actual
> hardware"
> rather than simulation?
>
> So step 2 is to check you are using the netlist simulator.
>
> Other than that, your code looks sensible,
>
> regards
>
> Alan
>
> --
> Alan Fitch
> HDL Consultant
>
> DOULOS - Developing Design Know-how
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