Re: I/Os with Cypress chip

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Brad,

Using the Cypress data, sheet I count 128 IO pins, 4 global clock pins
and 4 global control pins.  This does add up to 136 "IO" pins.
However, the global clock pins can be used only for clock signals and,
according to the data sheet, "There are four dedicated inputs
(GCTI[3:0]) that are used as Global Control Signals available to every
IO cell.  These global control signals may be used as output enables,
register resets, and register clock enables as shown in figure 8."  So
the global control signals are dedicated inputs and the global clocks
can be used only for clocks.  This should explain why you are not able
to use 136 pins for general purpose IO.

Best regards,

Charles

Re: I/Os with Cypress chip
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Brad,

I can't explain the loss of other I/O pins when the global signals are
used.  This could be a fitter problem.  If it is, I wish you the best
of luck trying to get Cypress to fix it.

We are having a number of difficulties with the 39K device fitter.
One of the scariest ones is this:  We successfully fitted a design and
then wished to make a change that involved adding a pin.  Since the
prototype board is already wired, we "fixed" the previously fitted
pins prior to fitting the design with the added pin.  The design does
not fit.  As a sanity check, we removed the new signal from the design
and tried to fit it with the pins "fixed" as the fitter previously
assigned them.  The design will not fit.  If we remove the compiler
directive that keeps the pinout from changing, the design will fit and
has the same pinout that we instructed it to keep.  This does not bode
well for future designs where one wants to make a change without
changing the pin assignments previously made.

I am sorry to report that Cypress seems unwilling to fix this and
several other problems with the 39K fitter.

Best regards,

Charles

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