Re: How to get 27MHz from 10 MHz in FPGA???

Of course, that's the way. I had misunderstood the problem as violating the min INPUT frequency... Sorry for the confusion. Peter Alfke

Followup to: By author: snipped-for-privacy@altera.com (Greg Steinke) In newsgroup: comp.arch.fpga

I've had problems with Quartus II 4.1 (Web Edition SP0-2) and getting the PLL values to make sense. In particular, if I feed it:

fin = 50 MHz c0 = 4/1 = 200 MHz c1 = 1/4 = 12.5 MHz

... it says it cannot make the desired PLL. 2.x and 3.x both did this correctly, and if I lie and specify fin = 75 MHz it builds the correct PLL and it works correctly with a 50 MHz input. The timing analyzer spits out a message that the input frequency has been overridden (by specifying clkin = 50 MHz as a timing constraint) and does the right thing.

This is for a Cyclone EP1C20F400C7 device.

-hpa

Hello Peter,

Quartus configures PLLs that satisfy all the device constraints (e.g. VCO range, PFD range, etc), which is why it cannot build the specific configuration you suggested for a Cyclone device (though it can be built in Stratix/StratixGX/StratixII devices).

In Cyclone devices, the VCO frequency must be between 490 Mhz and 1000 Mhz. For the example you gave, the resulting PLL's VCO frequency for a

75 Mhz input would be 600 Mhz (since the M counter is 8, and N counter is 1). But if you manually bypass this safeguard and feed in a frequency of 50 Mhz, the PLL's VCO frequency would be 400 Mhz, which is outside the supported range for Cyclone PLLs.

In the situation described above (75 Mhz input selected, but

50Mhz actual) the PLL is operating outside the specified range, so jitter performance and static phase shift may be adversely affected. This limit was set in Quartus II 3.0 SP2 for the first time, as a result of characterization of the Cyclone devices. Previously, in Quartus II 3.0, the limit was 300 Mhz, based on preliminary simulation results.

Hope this helps.

- Subroto Datta Altera Corp.