Re: FPGA Project Support

GREETINGS AND FELICITATIONS, MR G'MAIL -

I AM PROUD TO PRESENT MYSELF TO YOU AS NABALU "SKIPPY" UMBEKE, MINISTER OF DESIGN FOR THE EXALTED FEDERAL REPUBLIC OF NIGERIA IN ABUJA. IT IS FOR ME TO OFFER YOU A FINDING ARISING FROM UNUSUAL CIRCUMSTANCES. AN ENGINEER WORKING FOR OUR MINISTRY RECENTLY DECEASED HIMSELF, LEAVING IN HIS WAKE AN FPGA DESIGN FOR WHAT WE CALL IT SCALAR DOT PRODUCT. IN HAPPY HAPPENSTANCE, WE ALSO HAVE NOT PAID FOR THIS DESIGN APPURTENANCE, LEAVING OUR OFFICES WITH A DUE PAYMENT OF $24,500,000 (TWENTY FOUR POINT FIVE MILLION DOLLARS).

MR. G'MAIL, WOULD YOU BE WILLING TO DO US CONSIDERABLE SERVICE AND TAKE DESIGN AND EXCESS DOLLARS OFF OUR TABLE? WE CAN EASY TRANSFER BOTH TO YOU WITH IMMEDIACY IF YOU WOULD ONLY GIVE TO US YOUR BANK ACCOUNT NUMBERS, SOCIAL SECURITY NUMBER, AND ANY OTHER SUCH PRIVATE INFORMATIONS THAT YOU WOULD BE RELUCTANT TO EMIT TO ANYONE OTHER THAN A MINISTER OF DESIGN IN A FARAWAY LAND. AS SOON AS I USURP THIS INFORMATION FROM YOU, I WILL HASTILY TRANSFER TO YOU THE MONIES AND THE DESIGN BOTH. AS A SIGN OF OUR FAITH AND GOODWILL IN THIS BURGEONING BUSINESS RELATIONSHIP, WE WILL SEND TO YOU ALSO A DESIGN FOR A MOST EXCELLENT TRAFFIC LIGHT CONTROLLER.

YOURS IN THE EPITOME OF HUMBLE SINCERITY, NABULU UMBEKE MINISTER OF DESIGN

I understood him to be asking for a commercial tender.

I thought the the link was intersting. As a graduate student in ECE, I've taken every course my school offers related to configurable logic and haven't had anything this interesting offered. Not one class has included taking a design to hardware, I've had to do that on my own. The designs required for the classes have also been very small, bordering on trivial in the most challenging cases.

Oh, well, that's a cool thing about FPGAs - it's pretty easy to do it on your own. It's just that I could justify more time on it if I were getting credit...

Good job, University of Kansas!

Rick

rickc (a) rdrop com

Mr. Umbeke,

I'm sure the original poster thanks you for your kind offer of assistance. As it happens, I also have come into possession of much knowledge through my years of experience. Perhaps it would be possible for us to coagulate our knowledge to help this poor unfortunate student. I would be glad, nay enthralled, to share my portion of a useful design for a mere 30% of the total moneys involved.

Yours, to the attainment of higher knowledge,

RB

P.S. Great post, Bob. Sorry I can't do it justice.

Should you wish to get a complete, working design, please answer privately so I can give you my Paypal ID.

Anyway, here is how I would do it. I will provide two solutions.

Solution #1 : "the works". Your teacher will bow before your m4d skillZ.

"dot product" core is an OPB master. Microblaze writes into "dot product" core's registers, information about where to grab the data in memory (vector 1 address, vector 2 address, vector length). "dot product" core acts as an OPB DMA master and burst-reads vector data, computes dot product, and wakes Microblaze up with an interrupt when it's done. Microblaze will then read result in "dot product" core's register. For added points, add provision for partitioned convolution.

Solution #2 : damn, get this over with. Vector data is stored in opb_bram memory. Memory is dual port, so one port is connected to OPB via standard Xilinx opb_bram core. Standard Xilinx central_dma core is used to copy vector data from SDRAM into the dedicated BRAM. Microblaze writes into "dot product" core's registers, information about where to grab the data in BRAM (vector 1 address, vector

2 address, vector length). "dot product" core hits BRAM and reads vector data, computes dot product, and wakes Microblaze up with an interrupt when it's done. Microblaze will then read result in "dot product" core's register.