Re: Everything need a reset?

always @ (posedge(clkin))

> clkout > above is a single clk_div module, but when I do simulation, I can't get it > work. > I know the reason. without a reset signal to give it a initial value of

'0'

or '1', the clkout will keep the value 'x' during simulation. > but there's no 'x' in FPGA or CPLD, the clkout will get whatever a value > after power up, and it can get work without additional reset.

There are designs that in reality don't need a reset, but do in simulation. Others need a reset in both cases.

-- glen

Reply to
Glen Herrmannsfeldt
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Really good idea. but it can't cover all the situation, when I want to divide the clock by 4,

8... maybe use glbl.GSR is a common solution. "jetmarc" ??????: snipped-for-privacy@posting.google.com...

'0'

Reply to
Jay

I change the code to reg clkout; wire GSR;

always@(posedge clkin) begin if(GSR == 1) clkout

Reply to
Yu Haiwen

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