always @ (posedge(clkin))
> clkout
> above is a single clk_div module, but when I do simulation, I can't get it
> work.
> I know the reason. without a reset signal to give it a initial value of
'0'
or '1', the clkout will keep the value 'x' during simulation.
> but there's no 'x' in FPGA or CPLD, the clkout will get whatever a value
> after power up, and it can get work without additional reset.
There are designs that in reality don't need a reset, but do in simulation. Others need a reset in both cases.
-- glen