Re: Dynamic Reconfiguration, Virtex II Pro

Hi tk,

thanks for your reply.

I had to get more familiar with the the buff-stuff. An ibufg is just a dedicated input buffer for connecting to the clock buffer BUFG or CLKDLL.The clock problem was solved with the insertion of a BUFG.

Actually, my dwarfish design is routed on a Virtex-II device using the Xilinx xapp290 example bus-macro. Maybe the format of that macro (created with a former FPGA-Editor version) differs slightly from the format of the self-made macros?

Christian

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Christian Haase
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