Your design should fit going from the 9500 to the 9500xl. The 9500xl actually has more function block fanin (36 to 54!) so I would think that there should be no fitting issues. The only architectural features lost are macrocell feedback and wire-anding in the AIM. The loss of macrocell feedback should be made up for by the additional FB inputs. The loss of wire-anding would cause your PTerm requirements to increase. Perhaps if you were near the maximum utilization for this it would not fit.
You may want to try contacting the Xilinx hotline. They are willing to try fitting close designs.
Arthur
I hope Google won't eat the first reply, so here's an addition to it,
> some parts of fitter report are below:
>
> > I have a design (admittedly making heavy use of the device resources)
> > which successfully fits into an XC9536 but not an XC9536XL. This is
> > something I hadn't anticipated when migrating to the newer part. Is
> > this to be expected, and is it likely that by tweaking any fitter
> > options (or otherwise) I will be able to get the design to fit ?
> >
> > I am using Xilinx Foundation F4.2i, Build 3.1.196.
> >
> > Richard.
> >
formatting link
>
>
> cpldfit: version E.33 Xilinx Inc.
> Fitter Report
> Design Name: iw Date: 4- 1-2003,
> 4:17AM
> Device Used: XC95144XL-5-TQ144
> Fitting Status: Successful
>
> **************************** Resource Summary
> ****************************
>
> Macrocells Product Terms Registers Pins Function
> Block
> Used Used Used Used Inputs
> Used
> 143/144 ( 99%) 558 /720 ( 77%) 100/144 ( 69%) 111/117 ( 94%) 415/432
> ( 96%)
>
> PIN RESOURCES:
>
> Signal Type Required Mapped | Pin Type Used
> Remaining
> ------------------------------------|---------------------------------------
> Input : 58 58 | I/O : 104
> 5
> Output : 44 44 | GCK/IO : 2
> 1
> Bidirectional : 8 8 | GTS/IO : 4
> 0
> GCK : 1 1 | GSR/IO : 1
> 0
> GTS : 0 0 |
> GSR : 0 0 |
> ---- ----
> Total 111 111
>
> *********************Function Block Resource
> Summary***********************
> Function # of FB Inputs Signals Total O/IO
> IO
> Block Macrocells Used Used Pt Used Req
> Avail
> FB1 18 53 53 67 12/0
> 15
> FB2 18 53 53 57 7/0
> 15
> FB3 18 51 51 87 14/0
> 15
> FB4 18 51 51 71 0/1
> 15
> FB5 18 52 52 83 8/0
> 14
> FB6 18 52 52 72 1/7
> 13
> FB7 18 51 51 66 0/0
> 15
> FB8 17 52 52 55 2/0
> 15
> ---- ----- -----
> -----
> 143 558 44/8
> 117
>
> So, in dense design you can't rely on Xilinx tools only, I was always
> 1-2 cells over 144 when I was playing with options, so I had to
> constrain things myself...