Hi James,
Can you tell me specifically what document you are looking at (document number, version, date)? I looked at Spartan-3 and Spartan-3E data sheets on the Xilinx website and Figure 18 (in either document) wasn't related to clocks.
The global clock distribution networks in the FPGA are driven by "global clock buffers". In the Spartan-3 families, it happens that "global clock buffers" are BUFGMUX. If you call out a BUFG in your design, it is transformed into a BUFGMUX by the MAP program (with the unused inputs of the BUFGMUX tied to appropriate constants...) These global resources are located at the top center and bottom center of the device. Spartan-3E, specifically, has some additional BUFGMUX on the left and right sides -- they are not fully global but still very useful.
You can route a signal to a BUFGMUX, and then onto the global clock distribution network. It can come from anywhere -- a DCM, another BUFGMUX, some internal logic, or from an I/O pin. It is a flexible arrangement.
If you have specific requirements for FPGA pin-to-pin timing (chip-level setup, hold, and clock to out) you will want to pay attention to which resources you use and where they are located with respect to each other so that you obtain the best performance possible.
Hope that helps, Eric