Re: ASIC divider in FPGA?

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Algorithms like that used in the IBM 360/91 or Cray-1 could be implemented
as combinatorial dividers.   An iterative algorithm like the 360/91, or
fully pipelined like the Cray-1 could also be implemented depending on the
required speed and available clock.

Possibly implemented in combination with the block RAM a reasonably
efficient implementation might be possible.

-- glen

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