Re: Altera ACEX 1K IOE

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Yeah - been there, done that - I had great fun making a 10KE do a 100MHz
SDRAM interface meet timing, due to the single flipflop :-(  Someone once
described the 10KE datasheet to me as "less than totally transparent" or
some such.  

The other gotcha is the implication that there is an asynch
preset on the FF - in the text it then describes that the P&R software
will automatically put an invertor fore and aft of the FF and use the
async reset input (that does exist).  Making a bit of a hash of your
tco as a a result :-(  

I was not a happy bunny that day, and from that day forward have made
a point of not looking at Altera's diagrams only reading the text...

Commiserations :-(

Martin

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TRW Conekt, Solihull, UK
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